ZHCSJX8B August   2018  – July 2019 TLV803E , TLV809E

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      典型应用
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagram
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
      2. 8.3.2 VDD Hysteresis
      3. 8.3.3 VDD Glitch Immunity
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active Low
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 VDD Between VPOR and VDD(min)
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 相关链接
    4. 12.4 接收文档更新通知
    5. 12.5 社区资源
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Pin Configuration and Functions

DBZ Package (Pin 1 = GND)
3-Pin SOT-23
Top View
TLV803E TLV809E pinout-01-DBZ-pkg-SLVSES2.gif
DCK Package
3-Pin SC-70
Top View
TLV803E TLV809E pinout-01-DCK-pkg-SLVSES2.gif
DBZ Package (Pin 1 = RESET, reverse pinout)
3-Pin SOT-23
Top View
TLV803E TLV809E pinout-01-DBZ-inv-pkg-SLVSES2.gif

Pin Functions

PIN I/O DESCRIPTION
NAME DCK, DBZ RDBZ (Reverse pinout)
GND 1 2 Ground
RESET 2 1 O Active low output reset signal: This pin is driven low logic when VDD voltage falls below the negative voltage threshold (VIT–). RESET remains low (asserted) for the delay time period (tD) after VDD voltage rise above VIT+.
VDD 3 3 I Input supply voltage. TLV80xE monitors VDD voltage