ADVANCE INFORMATION for pre-production products; subject to change without notice.
RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT–). If VDD falls below the negative threshold (VIT–), then reset is asserted and RESET goes to low impedance pulling output low VOL.
When VDD rise above VIT+, the delay circuit will hold RESET low for the specified reset delay period (tD). When the reset delay has elapsed the RESET pin goes back to high impedance and output goes high voltage (VOH).
The open drain version requires a pull-up resistor to hold RESET pin high, connect the pull-up resistor to the desired interface voltage logic, RESET can be pulled up to any voltage up to max voltage independent of the VDD voltage. To ensure proper voltage levels, give some consideration when choosing the pull-up resistor values. The pull-up resistor value is determined by VOL, the output capacitive loading, and the output leakage current (ILKG(OD)).
The push-pull variant does not require a pull-up resistor.