ZHCS187C April   2011  – September 2015 TLV803 , TLV853

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD Transient Rejection
      2. 8.3.2 Reset During Power Up and Power Down
      3. 8.3.3 Bidirectional Reset Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > Power-Up Reset Voltage)
      2. 8.4.2 Power On Reset (VDD < Power-Up Reset Voltage)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Monitoring Multiple Supplies
      2. 9.1.2 Output Level Shifting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
        1. 12.1.1.1 评估模块
        2. 12.1.1.2 Spice 模型
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 相关链接
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Detailed Description

Overview

The TLV803 family of supervisory circuits provides circuit initialization and timing supervision. The TLV853 and TLV863 are both functionally equivalent to the TLV803. These devices output a logic low whenever VDD drops below the negative-going threshold voltage (VIT–). The output, RESET, remains low for approximately 200 ms after the VDD voltage exceeds the positive-going threshold voltage (VIT– + Vhys). These devices are designed to ignore fast transients on the VDD pin.

Functional Block Diagram

TLV803 TLV853 TLV863 fbd_bvs157.gif

Feature Description

VDD Transient Rejection

The TLV803 has built-in rejection of fast transients on the VDD pin. The rejection of transients depends on both the duration and the amplitude of the transient. The amplitude of the transient is measured from the bottom of the transient to the negative threshold voltage of the TLV803, as shown in Figure 8.

TLV803 TLV853 TLV863 ai_transient_bvs157.gif Figure 8. Voltage Transient Measurement

The TLV803 does not respond to transients that are fast duration/low amplitude or long duration/small amplitude. Figure 5 shows the relationship between the transient amplitude and duration needed to trigger a reset. Any combination of duration and amplitude above the curve generates a reset signal.

Reset During Power Up and Power Down

The TLV803 output is valid when VDD is greater than 1.1 V. When VDD is less than 1.1 V, the output transistor turns off and becomes high impedance. The voltage on the RESET pin rises to the voltage level connected to the pull-up resistor. Figure 9 shows a typical waveform for power-up, assuming the RESET pin has a pull-up resistor connected to the VDD pin.

TLV803 TLV853 TLV863 ai_power-up_bvs157.gif Figure 9. Power-Up Response

Bidirectional Reset Pins

Some microcontrollers have bidirectional reset pins that act as both inputs and outputs. In a situation where the TLV803 is pulling the RESET line low while the microcontroller is trying the force the RESET line high, a series resistor should be placed between the output of the TLV803 and the RESET pin of the microcontroller to protect against excessive current flow. Figure 10 shows the connection of the TLV803 to a microcontroller using a series resistor to drive a bidirectional RESET line.

TLV803 TLV853 TLV863 ai_reset_pin_bvs157.gif Figure 10. Connection To Bidirectional Reset Pin

Device Functional Modes

Normal Operation (VDD > Power-Up Reset Voltage)

When the voltage on VDD is greater than 1.1 V, the RESET signal asserts when VDD is less than VIT– and deasserts when VDD is greater thanVIT–.

Power On Reset (VDD < Power-Up Reset Voltage)

When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (power-up reset voltage), both outputs are in a high-impedance state.