ZHCS187C April   2011  – September 2015 TLV803 , TLV853

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD Transient Rejection
      2. 8.3.2 Reset During Power Up and Power Down
      3. 8.3.3 Bidirectional Reset Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > Power-Up Reset Voltage)
      2. 8.4.2 Power On Reset (VDD < Power-Up Reset Voltage)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Monitoring Multiple Supplies
      2. 9.1.2 Output Level Shifting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
        1. 12.1.1.1 评估模块
        2. 12.1.1.2 Spice 模型
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 相关链接
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Pin Configuration and Functions

TLV803: DBZ Package
3-Pin SOT-23
Top View
TLV803 TLV853 TLV863 po_803_dbz_sbvs157.gif
TLV853: DBZ Package
3-Pin SOT-23
Top View
TLV803 TLV853 TLV863 po_853_dbz_sbvs157.gif
TLV863: DBZ Package
3-Pin SOT-23
Top View
TLV803 TLV853 TLV863 po_863_dbz_sbvs157.gif

Pin Functions

PIN I/O DESCRIPTION
NAME TLV803 TLV853 TLV863
GND 1 2 3 Ground pin.
RESET 2 1 1 O RESET is an open-drain output that is driven to a low impedance state when RESET is asserted. RESET remains low (asserted) for the delay time (td) after VDD exceeds VIT–. Use a 10-kΩ to 1-MΩ pullup resistor on this pin. The pullup voltage is not limited by VDD.
VDD 3 3 2 I Supply voltage pin. It is good analog design practice to place a 0.1-µF ceramic capacitor close to this pin.