ZHCSE78A December   2011  – September 2015 TLV320AIC3262

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics, SAR ADC
    6. 8.6  Electrical Characteristics, ADC
    7. 8.7  Electrical Characteristics, Bypass Outputs
    8. 8.8  Electrical Characteristics, Microphone Interface
    9. 8.9  Electrical Characteristics, Audio DAC Outputs
    10. 8.10 Electrical Characteristics, Class-D Outputs
    11. 8.11 Electrical Characteristics, Miscellaneous
    12. 8.12 Electrical Characteristics, Logic Levels
    13. 8.13 I2S/LJF/RJF Timing in Master Mode (see )
    14. 8.14 I2S/LJF/RJF Timing in Slave Mode (see )
    15. 8.15 DSP/Mono PCM Timing in Slave Mode (see )
    16. 8.16 I2C Interface Timing (see )
    17. 8.17 SPI Interface Timing
    18. 8.18 Dissipation Ratings
    19. 8.19 Typical Characteristics
      1. 8.19.1 Audio ADC Performance
      2. 8.19.2 Audio DAC Performance
      3. 8.19.3 Class-D Driver Performance
      4. 8.19.4 MICBIAS Performance
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Digital Pins
      2. 10.3.2  Analog Pins
      3. 10.3.3  Multifunction Pins
      4. 10.3.4  Analog Audio I/O
        1. 10.3.4.1  Analog Low Power Bypass
        2. 10.3.4.2  ADC Bypass Using Mixer Amplifiers
        3. 10.3.4.3  Headphone Outputs
        4. 10.3.4.4  Using the Headphone Amplifier
        5. 10.3.4.5  Ground-Centered Headphone Amplifier Configuration
        6. 10.3.4.6  Circuit Topology
        7. 10.3.4.7  Charge Pump Set-Up and Operation
        8. 10.3.4.8  Output Power Optimization
        9. 10.3.4.9  Offset Correction and Start-Up
        10. 10.3.4.10 Ground-Centered Headphone Setup
          1. 10.3.4.10.1 High Audio Output Power, High Performance Setup
          2. 10.3.4.10.2 High Audio Output Power, Low Power Consumption Setup
          3. 10.3.4.10.3 Medium Audio Output Power, High Performance Setup
          4. 10.3.4.10.4 Lowest Power Consumption, Medium Audio Output Power Setup
        11. 10.3.4.11 Stereo Unipolar Configuration
          1. 10.3.4.11.1 Circuit Topology
          2. 10.3.4.11.2 Unipolar Turn-On Transient (Pop) Reduction
        12. 10.3.4.12 Mono Differential DAC to Mono Differential Headphone Output
        13. 10.3.4.13 Stereo Line Outputs
        14. 10.3.4.14 Line Out Amplifier Configurations
        15. 10.3.4.15 Differential Receiver Output
        16. 10.3.4.16 Stereo Class-D Speaker Outputs
      5. 10.3.5  ADC / Digital Microphone Interface
        1. 10.3.5.1 ADC Processing Blocks - Overview
          1. 10.3.5.1.1 ADC Processing Blocks
      6. 10.3.6  DAC
        1. 10.3.6.1 DAC Processing Blocks — Overview
          1. 10.3.6.1.1 DAC Processing Blocks
      7. 10.3.7  Powertune
      8. 10.3.8  Clock Generation and PLL
      9. 10.3.9  Interfaces
        1. 10.3.9.1 Control Interfaces
          1. 10.3.9.1.1 I2C Control
          2. 10.3.9.1.2 SPI Control
        2. 10.3.9.2 Digital Audio Interfaces
        3. 10.3.9.3 miniDSP
          1. 10.3.9.3.1 miniDSP
          2. 10.3.9.3.2 Software
        4. 10.3.9.4 Asynchronous Sample Rate Conversion (ASRC)
      10. 10.3.10 Device Special Functions
      11. 10.3.11 Device Power Consumption
      12. 10.3.12 Powertune
      13. 10.3.13 Clock Generation and PLL
      14. 10.3.14 Interfaces
        1. 10.3.14.1 Control Interfaces
        2. 10.3.14.2 I2C Control
        3. 10.3.14.3 SPI Control
        4. 10.3.14.4 Digital Audio Interfaces
      15. 10.3.15 miniDSP
      16. 10.3.16 Device Special Functions
    4. 10.4 Device Functional Modes
      1. 10.4.1 Recording Mode
      2. 10.4.2 Playback Mode
      3. 10.4.3 Analog Low Power Bypass Modes
    5. 10.5 Register Maps
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Charge Pump Flying and Holding Capacitor
        2. 11.2.2.2 Reference Filtering Capacitor
        3. 11.2.2.3 MICBIAS
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
    1. 12.1 Device Power Consumption
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Examples
  14. 14器件和文档支持
    1. 14.1 文档支持
      1. 14.1.1 相关文档
    2. 14.2 社区资源
    3. 14.3 商标
    4. 14.4 静电放电警告
    5. 14.5 Glossary
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Detailed Description

10.1 Overview

The TLV320AIC3262 is a flexible, highly-integrated, low-power, low-voltage stereo audio codec with digital microphone inputs and programmable outputs, PowerTune capabilities, selectable audio-processing blocks, fixed predefined and parameterizable signal processing blocks, integrated PLL, and flexible digital audio interfaces. It is intended for applications in mobile handsets, tablets, eBooks, portable navigation devices, portable media player, portable gaming systems and portable computing. Available in a 4.81 mm x 4.81 mm 81-ball WCSP (YZF) Package, the device includes an extensive register-based control of power, input and output channel configuration, gains, effects, pin-multiplexing, and clocks, allowing the codec to be precisely targeted to its application.

The TLV320AIC3262 consists of the following blocks:

  • 5.6-mW Stereo Audio ADC with 93dB SNR
  • 2.7-mW Stereo 48kHz DAC Playback
  • 30-mW DirectPath Headphone Driver
  • 128-mW Differential Receiver Output Driver
  • Stereo Class-D Speaker Drivers
  • Programmable 12-Bit SAR ADC
  • SPI and I2C Control Interfaces
  • Three Independent Digital Audio Serial Interfaces
  • Programmable PLL Generator
  • Fully-Programmable Enhanced miniDSP with PurePath Studio Support

The TLV320AIC3262 features PowerTune to trade power dissipation versus performance. This mechanism has many modes that can be selected at the time of device configuration.

10.2 Functional Block Diagram

TLV320AIC3262 B0395-04_LAS679_v6b.gif

10.3 Feature Description

10.3.1 Digital Pins

Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a default function, and also can be reprogrammed to cover alternative functions for various applications.

The fixed-function pins are hardware-control pins RESET and SPI_SELECT pin. Depending on the state of SPI_SELECT, four pins SCL, SDA, GPO1, and GPI1 are configured for either I2C or SPI protocol. Only in I2C mode, GPI3 and GPI4 provide four possible I2C addresses for the TLV320AIC3262.

Other digital IO pins can be configured for various functions through register control.

10.3.2 Analog Pins

Analog functions can also be configured to a large degree. For minimum power consumption, analog blocks are powered down by default. The blocks can be powered up with fine granularity according to the application needs.

The possible analog routings of analog input pins to ADCs and output amplifiers as well as the routing from DACs to output amplifiers can be seen in the Analog Routing Diagram.

10.3.3 Multifunction Pins

Table 1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be programmed to be any of 9 pins (MCLK1, MCLK2, BCLK1, DIN1, BCLK2, GPIO1, GPIO2, GPI1, GPI2).

Table 1. Multifunction Pin Assignments for Pins MCLK1, MCLK2, WCLK1, BCLK1, DIN1, DOUT1, WCLK2, BCLK2, DIN2, and DOUT2

1 2 3 4 5 6 7 8 9 10
PIN FUNCTION MCLK1 MCLK2 WCLK1 BCLK1 DIN1 DOUT1 WCLK2 BCLK2 DIN2 DOUT2
A INT1 Output E E E E
B INT2 Output E E E E
C SAR ADC Interrupt E E E E
D CLOCKOUT Output E E E E
E ADC_MOD_CLOCK Output E E E
F Single DOUT for ASI1 (All Channels) E, D
F Single DOUT for ASI2 E, D
F Single DOUT for ASI3
G Multiple DOUTs for ASI1 (L1, R1) E
G Multiple DOUTs for ASI1 (L2, R2) E
G Multiple DOUTs for ASI1 (L3, R3) E
G Multiple DOUTs for ASI1 (L4, R4) E
I General Purpose Output (via Reg) E(4) E E E
F Single DIN for ASI1 (All Channels) E, D(3)
F Single DIN for ASI2 E, D
F Single DIN for ASI3
H Multiple DINs for ASI1 (L1, R1) E
H Multiple DINs for ASI1 (L2, R2) E
H Multiple DINs for ASI1 (L3, R3) E E
H Multiple DINs for ASI1 (L4, R4) E E
J Digital Mic Data E E E
K Input to PLL_CLKIN S(1), D S S(2) S S(2)
L Input to ADC_CLKIN S(1), D S S(2) S(2)
M Input to DAC_CLKIN S(1), D S S(2) S(2)
N Input to CDIV_CLKIN S(1), D S S S S
O Input to LFR_CLKIN S(1), D S S S S S
P Input to HF_CLK S(1)
Q Input to REF_1MHz_CLK S(1)
R General Purpose Input (via Reg) E E E E
S ISR Interrupt for miniDSP (via Reg) E
T WCLK Output for ASI1 E
U WCLK Input for ASI1 S, D
V BCLK Output for ASI1 E
W BCLK Input for ASI1 S(2), D
X WCLK Output for ASI2 E
Y WCLK Input for ASI2 S, D
Z BCLK Output for ASI2 E
AA BCLK Input for ASI2 S(2), D
BB WCLK Output for ASI3
CC WCLK Input for ASI3
DD BCLK Output for ASI3
EE BCLK Input for ASI3
(1) S(3): The MCLK1 pin could be chosen to drive the PLL, ADC Clock, DAC Clock, CDIV Clock, LFR Clock, HF Clock, and REF_1MHz_CLK inputs simultaneously
(2) S(4): The BCLK1 or BCLK2 pins could be chosen to drive the PLL, ADC Clock, DAC Clock, and audio interface bit clock inputs simultaneously
(3) D: Default Function
(4) E: The pin is exclusively used for this function, no other function can be implemented with the same pin (for example if DOUT1 has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time)

Table 2. Multifunction Pin Assignments for Pins WCLK3, BCLK3, DIN3, DOUT3, GPIO1, GPIO2, GPO1, GPI1, GPI2, GPI3, and GPI4

11 12 13 14 15 16 17 18 19 20 21
PIN FUNCTION WCLK3 BCLK3 DIN3 DOUT3 GPIO1 GPIO2 GPO1/
MISO(4)		 GPI1/
SCLK(4)		 GPI2 GPI3(5) GPI4(5)
A INT1 Output E E E
B INT2 Output E E E
C SAR ADC Interrupt E E E
D CLOCKOUT Output E E E
E ADC_MOD_CLOCK Output E E E
F Single DOUT for ASI1 (All Channels) E
F Single DOUT for ASI2
F Single DOUT for ASI3 E, D
G Multiple DOUTs for ASI1 (L1, R1)
G Multiple DOUTs for ASI1 (L2, R2) E E E
G Multiple DOUTs for ASI1 (L3, R3) E E E E E
G Multiple DOUTs for ASI1 (L4, R4) E E E E
I General Purpose Output (via Reg) E(3) E E E E E
F Single DIN for ASI1 (All Channels) E
F Single DIN for ASI2
F Single DIN for ASI3 E, D
H Multiple DINs for ASI1 (L1, R1)
H Multiple DINs for ASI1 (L2, R2) E E E
H Multiple DINs for ASI1 (L3, R3) E E E E E
H Multiple DINs for ASI1 (L4, R4) E E E E
J Digital Mic Data E E E E
K Input to PLL_CLKIN S(1) S(1) S(1) S(1)
L Input to ADC_CLKIN S(1) S(1) S(1) S(1)
M Input to DAC_CLKIN S(1) S(1) S(1) S(1)
N Input to CDIV_CLKIN S S
O Input to LFR_CLKIN S S S S S S
P Input to HF_CLK
Q Input to REF_1MHz_CLK
R General Purpose Input (via Reg) E E E E E E E
S ISR Interrupt for miniDSP (via Reg) E E E
T WCLK Output for ASI1 E E
U WCLK Input for ASI1 E
V BCLK Output for ASI1 E
W BCLK Input for ASI1 E
X WCLK Output for ASI2
Y WCLK Input for ASI2
Z BCLK Output for ASI2
AA BCLK Input for ASI2
BB WCLK Output for ASI3 E
CC WCLK Input for ASI3 S, D(2)
DD BCLK Output for ASI3 E
EE BCLK Input for ASI3 S, D
FF ADC BCLK Input for ASI1 E E E E E E
GG ADC WCLK Input for ASI1 E E E E E E
HH ADC BCLK Output for ASI1 E E
II ADC WCLK Output for ASI1 E E
JJ ADC BCLK Input for ASI2 E E E E E E
KK ADC WCLK Input for ASI2 E E E E E E
LL ADC BCLK Output for ASI2 E E
MM ADC WCLK Output for ASI2 E E
NN ADC BCLK Input for ASI3 E E E E E E
OO ADC WCLK Input for ASI3 E E E E E E
PP ADC BCLK Output for ASI3 E E
QQ ADC WCLK Output for ASI3 E E
(1) S(4): The GPIO1, GPIO2, GPI1, or GPI2 pins could be chosen to drive the PLL, ADC Clock, and DAC Clock inputs simultaneously
(2) D: Default Function
(3) E: The pin is exclusively used for this function, no other function can be implemented with the same pin (for example if WCLK3 has been allocated for General Purpose Output, it cannot be used as the ASI3 WCLK output at the same time)
(4) GPO1 and GPI1 can only be utilized for functions defined in this table when part utilizes I2C for control. In SPI mode, these pins serve as the MISO and SCLK, respectively.
(5) GPI3 and GPI4 can only be utilized for functions defined in this table when part utilizes SPI for control. In I2C mode, these pins serve as I2C address pins.

10.3.4 Analog Audio I/O

TLV320AIC3262 AIC3262_analog_routing_v1_2b.gif
For more detailed information see the TLV320AIC3262 Application Reference Guide, SLAU309.
Figure 20. Analog Routing Diagram

10.3.4.1 Analog Low Power Bypass

The TLV320AIC3262 offers two analog-bypass modes. In either of the modes, an analog input signal can be routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC resources are required for such operation; this supports low-power operation during analog-bypass mode. In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1L to the left lineout amplifier (LOL) and IN1R to LOR. Additionally, line-level signals can be routed directly from these analog inputs to the differential receiver amplifier, which outputs on RECP and RECM.

10.3.4.2 ADC Bypass Using Mixer Amplifiers

In addition to the low-power bypass mode, there is a bypass mode that uses the programmable gain amplifiers of the input stage in conjunction with a mixer amplifier. With this mode, microphone-level signals can be amplified and routed to the line, speaker, or headphone outputs, fully bypassing the ADC and DAC. To enable this mode, the mixer amplifiers are powered on via software command.

10.3.4.3 Headphone Outputs

The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16 Ω in single-ended DC-coupled headphone configurations. An integral charge pump generates the negative supply required to operate the headphone drivers in DC-coupled mode, where the common mode of the output signal is made equal to the ground of the headphone load using a ground-sense circuit. Operation of headphone drivers in DC-coupled (ground centered mode) eliminates the need for large DC-blocking capacitors.

TLV320AIC3262 s_3262_gchp_out_NEW.gif Figure 21. TLV320AIC3262 Ground-Centered Headphone Output

Alternatively the headphone amplifier can also be operated in a unipolar circuit configuration using DC blocking capacitors.

10.3.4.4 Using the Headphone Amplifier

The headphone drivers are capable of driving a mixed combination of DAC signal, left and right ADC PGA signal, and LOL and LOR output signals by configuring B0_P1_R27-R29. The ADC PGA signals can be attenuated up to 36 dB before routing to headphone drivers by configuring B0_P1_R18 and B0_P1_R19. The line-output signals can be attenuated up to 78 dB before routing to headphone drivers by configuring B0_P1_R28 and B0_P1_R29. The level of the DAC signal can be controlled using the digital volume control of the DAC by configuring B0_P0_R64-R66. To control the output-voltage swing of headphone drivers, the headphone driver volume control provides a range of –6.0 dB to +14.0 dB(1) in steps of 1 dB. These can be configured by programming B0_P1_R27, B0_P1_R31, and B0_P1_R32. In addition, finer volume controls are also available when routing LOL or LOR to the headphone drivers by controlling B0_P1_R27-R28. These level controls are not meant to be used as dynamic volume control, but more to set output levels during initial device configuration. Register B0_P1_R9_D[6:5] allows the headphone output stage to be scaled to tradeoff power delivered versus quiescent power consumption. (1)

(1)If the device must be placed into 'mute' from the –6.0-dB setting, set the device at a gain of –5.0 dB first, then place the device into mute.

10.3.4.5 Ground-Centered Headphone Amplifier Configuration

Among the other advantages of the ground-centered connection is inherent freedom from turnon transients that can cause audible pops, sometimes at uncomfortable volumes.

10.3.4.6 Circuit Topology

The power supply hook up scheme for the ground centered configuration is shown in HVDD_18 pin supplies the positive side of the headphone amplifier. CPVDD_18 pin supplies the charge pump which in turn supplies the negative side of the headphone amplifier. Two capacitors are required for the charge pump circuit to work. These capacitors should be X7R rated.

TLV320AIC3262 f_3262_gc_hp_out.gif Figure 22. Ground-Centered Headphone Connections

10.3.4.7 Charge Pump Set-Up and Operation

The built-in charge pump draws charge from the CPVDD_18 supply, and by switching the external capacitor between CPFCP and CPFCM, generates the negative voltage on VNEG pin. The charge-pump circuit uses the principles of switched-capacitor charge conservation to generate the VNEG supply in a very efficient fashion.

To turn on the charge pump circuit when headphone drivers are powered, program B0_P1_R35_D[1:0] to 00. When the charge pump circuit is disabled, VNEG acts as a ground pin, allowing unipolar configuration of the headphone amps. By default, the charge pump is disabled. The switching rate of the charge pump can be controlled by B0_P1_R33. Because the charge pump can demand significant inrush currents from the supply, it is important to have a capacitor connected in close proximity to the CPVDD_18 and CPVSS pins of the device. At 500-kHz clock rate this requires approximately a 10-μF capacitor. The ESR and ESL of the capacitor must be low to allow fast switching currents.

The ground-centered mode of operation is enabled by configuring B0_P1_R31_D7 to 1. The HPL and HPR gain settings are ganged in Ground-Cetered Mode of operation (B0_P1_R32_D7 = 1). The HPL and HPR gain settings cannot be ganged if using the Stereo Unipolar Configuration.

10.3.4.8 Output Power Optimization

The device can be optimized for a specific output-power range. The charge pump and the headphone driver circuitry can be reduced in power so less overall power is consumed. The headphone driver power can be programmed in B0_P1_R9. The control of charge pump switching current is programmed in B0_P1_R34_D[4:2].

10.3.4.9 Offset Correction and Start-Up

The TLV320AIC3262 offers an offset-correction scheme that is based on calibration during power up. This scheme minimizes the differences in DC voltage between HPVSS_SENSE and HPL/HPR outputs.

The offset calibration happens after the headphones are powered up in ground-centered configuration. All other headphone configurations like signal routings, gain settings, and mute removal must be configured before headphone power-up. Any change in these settings while the headphones are powered up may result in additional offsets and are best avoided.

The offset-calibration block has a few programmable parameters that the user must control. The user can either choose to calibrate the offset only for the selected input routing or all input configurations. The calibration data is stored in internal memory until the next hardware reset or until AVDDx power is removed.

Programming B0_P1_R34_D[1:0] as 10 causes the offset to be calibrated for the selected input mode. Programming B0_P1_R34_D[1:0] as 11 causes the offset to be calibrated for all possible configurations. All related blocks must be powered while doing offset correction.

Programming B0_P1_R34_D[1:0] as 00 (default) disables the offset correction block. While the offset is being calibrated, no signal should be applied to the headphone amplifier, that is the DAC should be kept muted and analog bypass routing should be kept at the highest attenuation.

10.3.4.10 Ground-Centered Headphone Setup

There are four practical device setups for ground-centered operation, shown in Table 3:

Table 3. Ground-Centered Headphone Setup Performance Options

AUDIO OUTPUT POWER HIGH PERFORMANCE LOW POWER CONSUMPTION
16Ω 32Ω 600Ω 16Ω 32Ω 600Ω
High SNR 94 dB 97 dB 98 dB 91 dB 94 dB 95 dB
Output Power 25 mW 22 mW 1.4mW 24 mW 23 mW 1.5mW
Idle Power Consumption 23 mW 21 mW 19mW 20 mW 15 mW 12 mW
High-Output, High-Performance Setup High-Output, Low-Power Setup
Medium SNR 92.5 dB 93 dB 93.5 dB 80.5 dB 85.5 dB 85.5 dB
Output Power 16 mW 8.5 mW 0.5 mW 0.9 mW 1.5mW 0.1 mW
Idle Power Consumption 14 mW 12 mW 9.7 mW 8.0 mW 6.6mW 5.1 mW
Medium-Output, High-Performance Setup Medium-Output, Low-Power Setup

10.3.4.10.1 High Audio Output Power, High Performance Setup

This setup describes the register programming necessary to configure the device for a combination of high audio output power and high performance. To achieve this combination the parameters must be programmed to the values in Table 4. For the full setup script, see Table 4.

Table 4. Setup A - High Audio Output Power, High Performance

PARAMETER VALUE PROGRAMMING
CM 0.9 B0_P1_R8_D2 = "0"
PTM PTM_P3 B0_P1_R3_D[4:2] = "000", B0_P1_R4_D[4:2] = "000"
Processing Block 1 to 6,22,23,24 B0_P0_R60_D[4:0]
DAC OSR 128 B0_P0_R13 = 0x00, B0_P0_R14 = 0x80
HP sizing 100 B0_P1_R9_D[6:5] = "00"
Gain 5dB B0_P1_R31 = 0x85, B0_P1_R32 = 0x85
DVDD 1.8 Apply 1.26 to 1.95V
AVDDx_18, HVDD_18, CPVDD_18 1.8 Apply 1.8 to 1.95V

10.3.4.10.2 High Audio Output Power, Low Power Consumption Setup

This setup describes the register programming necessary to configure the device for a combination of high audio output power and low power consumption. To achieve this combination the parameters must be programmed to the values in Table 5. For the full setup script, see Table 5.

Table 5. Setup B - High Audio Output Power, Low Power Consumption

PARAMETER VALUE PROGRAMMING
CM 0.75 B0_P1_R8_D2 = "1"
PTM PTM_P2 B0_P1_R3_D[4:2] = "001", B0_P1_R4_D[4:2] = "001"
Processing Block 7 to 16 B0_P0_R60_D[4:0]
DAC OSR 64 B0_P0_R13 = 0x00, B0_P0_R14 = 0x40
HP sizing 100 B0_P1_R9_D[6:5] = "00"
Gain 12dB B0_P1_R31 = 0x8c, B0_P1_R32 = 0x8c
DVDD 1.26 Apply 1.26 to 1.95V
AVDDx_18, HVDD_18, CPVDD_18 1.8 Apply 1.5 to 1.95V

10.3.4.10.3 Medium Audio Output Power, High Performance Setup

This setup describes the register programming necessary to configure the device for a combination of medium audio output power and high performance. To achieve this combination the parameters must be programmed to the values in Table 6. For the full setup script, see Table 6.

Table 6. Setup C - Medium Audio Output Power, High Performance

PARAMETER VALUE PROGRAMMING
CM 0.75 B0_P1_R8_D2 = "1"
PTM PTM_P2 B0_P1_R3_D[4:2] = "001", B0_P1_R4_D[4:2] = "001"
Processing Block 7 to 16 B0_P0_R60_D[4:0]
DAC OSR 64 B0_P0_R13 = 0x00, B0_P0_R14 = 0x40
HP sizing 100 B0_P1_R9_D[6:5] = "00"
Gain 7dB B0_P1_R31 = 0x87, B0_P1_R32 = 0x87
DVDD 1.26 Apply 1.26 to 1.95V
AVDDx_18, HVDD_18, CPVDD_18 1.5 Apply 1.8 to 1.95V

10.3.4.10.4 Lowest Power Consumption, Medium Audio Output Power Setup

This setup describes the register programming necessary to configure the device for a combination of medium audio output power and lowest power consumption. To achieve this combination the parameters must be programmed to the values in Table 7. For the full setup script, see Table 7.

Table 7. Setup D - Lowest Power Consumption, Medium Audio Output Power

PARAMETER VALUE PROGRAMMING
CM 0.75 B0_P1_R8_D2 = "1"
PTM PTM_P1 B0_P1_R3_D[4:2] = "010", B0_P1_R4_D[4:2] = "010"
Processing Block 26 B0_P0_R60_D[4:0] = "1 1010"
DAC OSR 64 B0_P0_R13 = 0x00, B0_P0_R14 = 0x40
HP sizing 25 B0_P1_R9_D[6:5] = "11"
Gain 10dB B0_P1_R31 = 0x8a , B0_P1_R32 = 0x8a
DVdd 1.26 Apply 1.26 to 1.95V
AVDDx_18, HVDD_18, CPVDD_18 1.5 Apply 1.5 to 1.95V

10.3.4.11 Stereo Unipolar Configuration

10.3.4.11.1 Circuit Topology

The power supply hook up scheme for the unipolar configuration is shown in Figure 23. HVDD_18 terminal supplies the positive side of the headphone amplifier. The negative side is connected to ground potential (VNEG). It is recommended to connect the CPVDD_18 terminal to DVdd, although the charge pump must not be enabled while the device is connected in unipolar configuration.

TLV320AIC3262 s_3262_unipolar_hookup_NEW.gif Figure 23. Unipolar Stereo Headphone Circuit

The left and right DAC channels are routed to the corresponding left and right headphone amplifier. This configuration is also used to drive line-level loads. To enable cap-coupled mode, B0_P1_R31_D7 should be set to 0. Note that the recommended range for the HVDD_18 supply in cap-coupled mode (1.65V-3.6V) is different than the recommended range for the default ground-centered configuration (1.5V-1.95V). In cap-coupled mode only, the Headphone output common mode can be controlled by changing B0_P1_R8_D[4:3].

10.3.4.11.2 Unipolar Turn-On Transient (Pop) Reduction

The TLV320AIC3262 headphone drivers also support pop-free operation in unipolar, ac-coupled configuration. Because the HPL and HPR are high-power drivers, pop can result due to sudden transient changes in the output drivers if care is not taken. The most critical care is required while using the drivers as stereo single-ended capacitively-coupled drivers as shown in Figure 23. The output drivers achieve pop-free power-up by using slow power-up modes. Conceptually, the circuit during power-up can be visualized as

TLV320AIC3262 pop_free_los585.gif Figure 24. Conceptual Circuit for Pop-Free Power-up

The value of Rpop can be chosen by setting register B0_P1_R11_D[1:0].

Table 8. Rpop Values (External Cc = 47uF)

B0_P1_R11_D[1:0] Rpop VALUE
10 2 kΩ
01 6 kΩ
00 25 kΩ

To minimize audible artifacts, two parameters can be adjusted to match application requirements. The voltage Vload across Rload at the beginning of slow charging should not be more than a few mV. At that time the voltage across Rload can be determined as:

Equation 1. TLV320AIC3262 q-slowchg_las549.gif

For a typical Rload of 32Ω, Rpop of 6 kΩ or 25 kΩ will deliver good results (see Table 8 for register settings).

According to the conceptual circuit in Figure 24, the voltage on PAD will exponentially settle to the output common-mode voltage based on the value of Rpop and Cc. Thus, the output drivers must be in slow power-up mode for time T, such that at the end of the slow power-on period, the voltage on Vpad is very close to the common-mode voltage. The TLV320AIC3262 allows the time T to be adjusted to allow for a wide range of Rload and Cc by programming B0_P1_R11_D[5:2]. For the time adjustments, the value of Cc is assumed to be 47μF. N=5 is expected to yield good results.

Table 9. N Values (External Cc = 47 µF)

B0_P1_R11_D[5:2] Slow Charging Time = N * RC_Time_Constant (for Rpop and Cc = 47μF)
0000 N=0
0001 N=0.5
0010 N=0.625
0011 N=0.75
0100 N=0.875
0101 N=1.0
0110 N=2.0
0111 N=3.0
1000 N=4.0
1001 N=5.0 (Typical Value)
1010 N=6.0
1011 N=7.0
1100 N=8.0
1101 N=16 (Not valid for Rpop=25kΩ)
1110 N=24 (Not valid for Rpop=25kΩ)
1111 N=32 (Not valid for Rpop=25kΩ)

Again, for example, for Rload=32Ω, Cc=47μF and common mode of 0.9V, the number of time constants required for pop-free operation is 5 or 6. A higher or lower Cc value will require higher or lower value for N.

During the slow-charging period, no signal is routed to the output driver. Therefore, choosing a larger than necessary value of N results in a delay from power-up to signal at output. At the same time, choosing N to be smaller than the optimal value results in poor pop performance at power-up.

The signals being routed to headphone drivers (for example DAC, MAL, MAR, and IN1) often have DC offsets due to less-than-ideal processing. As a result, when these signals are routed to output drivers, the offset voltage causes a pop. To improve the pop-performance in such situations, a feature is provided to soft-step the DC-offset. At the beginning of the signal routing, a high-value attenuation can be applied which can be progressively reduced in steps until the desired gain in the channel is reached. The time interval between each of these gain changes can be controlled by programming B0_P1_R11_D[7:6]. This gain soft-stepping is applied only during the initial routing of the signal to the output driver and not during subsequent gain changes.

Table 10. Soft-Stepping Step Time

B0_P1_R11_D[7:6] SOFT-STEPPING STEP TIME DURING INITIAL SIGNAL ROUTING
00 0 ms (soft-stepping disabled)
01 50ms
10 100ms
11 200ms

It is recommended to use the following sequence for achieving optimal pop performance at power-up:

  1. Choose the value of Rpop, N (time constants) and soft-stepping step time for slow power-up.
  2. Choose the configuration for output drivers, including common modes and output stage power connections
  3. Select the signals to be routed to headphones.
  4. Power-up the blocks driving signals into HPL and HPR, but keep it muted
  5. Unmute HPL and HPR and set the desired gain setting.
  6. Power-on the HPL and HPR drivers.
  7. Unmute the block driving signals to HPL and HPR after the Driver PGA flags are set to indicate completion of soft-stepping after power-up. These flags can be read from B0_P1_R63_D[7:6].

It is important to configure the Headphone Output driver depop control registers before powering up the headphone; these register contents should not be changed when the headphone drivers are powered up.

Before powering down the HPL and HPR drivers, it is recommended that user read back the flags in B0_P1_R63. For example. before powering down the HPL driver, ensure that bit B0_P1_R63_D7 = 1 and bit B0_P1_R64_D7 = 1 if LOL is routed to HPL and bit B0_P1_R65_D5 = 1 if the Left Mixer is routed to HPL. The output driver should be powered down only after a steady-state power-up condition has been achieved. This steady state power-up condition also must be satisfied for changing the HPL/R driver mute control (setting both B0_P1_R31_D[5:0] and B0_P1_R32_D[5:0] to "11 1001"), that is, muting and unmuting should be done after the gain and volume controls associated with routing to HPL/R finished soft-stepping.

In the differential configuration of HPL and HPR, when no coupling capacitor is used, the slow charging method for pop-free performance need not be used. In the differential load configuration for HPL and HPR, it is recommended to not use the output driver MUTE feature, because a pop may result.

During the power-down state, the headphone outputs are weakly pulled to ground using an approximately 50kΩ resistor to ground, to maintain the output voltage on HPL and HPR terminals.

10.3.4.12 Mono Differential DAC to Mono Differential Headphone Output

TLV320AIC3262 lp_mon_hp_los585.gif Figure 25. Low Power Mono DAC to Differential Headphone

This configuration, available in unipolar configuration of the HP amplifier supplies, supports the routing of the two differential outputs of the mono, left channel DAC to the headphone amplifiers in differential mode (B0_P1_R27_D5 = 1 and B0_P1_R27_D2 = 1).

10.3.4.13 Stereo Line Outputs

The stereo line level drivers on LOL and LOR terminals can drive a wide range of line level resistive impedances in the range of 600Ω 10 kΩ. The output common mode of line level drivers can be configured to equal the analog input common-mode setting, either 0.75V or 0.9V. The line-level drivers can drive out a mixed combination of DAC signal and attenuated ADC PGA signal, and signal mixing is register-programmable.

10.3.4.14 Line Out Amplifier Configurations

Signal mixing can be configured by programming B0_P1_R22 and B0_P1_R23. To route the output of Left DAC and Right DAC for stereo single-ended output, as shown in Figure 26, LDACM can be routed to LOL driver by setting B0_P1_R22_D7 = 1, and RDACM can be routed to LOR driver by setting B0_P1_R22_D6 = 1. Alternatively, stereo single-ended signals can also be routed through the mixer amplifiers by configuring B0_P1_R23_D[7:6]. For lowest-power operation, stereo single-ended signals can also be routed in direct pin bypass with possible gains of 0 dB, –6 dB, or –12 dB by configuring B0_P1_R23_D[4:3] and B0_P1_R23_D[1:0]. While each of these two bypass cases could be used in a stereo single-ended configuration, a mono differential input signal could also be used.

The output of the stereo line out drivers can also be routed to the stereo headphone drivers, with 0 dB to –72-dB gain controls in steps of 0.5 dB on each headphone channel. This enables the DAC output or bypass signals to be simultaneously played back to the stereo headphone drivers as well as stereo line-level drivers. This routing and volume control is achieved in B0_P1_R28 and B0_P1_R29.

TLV320AIC3262 f_3262_stereo_se_line_out.gif Figure 26. Stereo Single-Ended Lineout

Additionally, the two line-level drivers can be configured to act as a mono differential line level driver by routing the output of LOL to LOR (B0_P1_R22_D2 = 1). This differential signal takes either LDACM, MAL, or IN1L-B as a single-ended mono signal and creates a differential mono output signal on LOL and LOR.

TLV320AIC3262 f_3262_se_in_to_diff_line_out.gif Figure 27. Single Channel Input to Differential Lineout

For digital outputs from the DAC, the two line-level drivers can be fed the differential output signal from the Right DAC by configuring B0_P1_R22_D5 = ‘1’.

TLV320AIC3262 f_3262_low_pwr_mono_dac_to_diff_line_out.gif Figure 28. Mono DAC Output to Differential Line-out

10.3.4.15 Differential Receiver Output

The differential receiver amplifier output spans the RECP and RECM pins and can drive a 32-Ω receiver driver. With output common-mode setting of 1.65V and RECVDD_33 supply at 3.3V, the receiver driver can drive up to a 1-Vrms output signal. With the RECVDD_33 supply at 3.3V, the receiver driver can deliver greater than 128mW into a 32Ω BTL load. If desired, the RECVDD_33 supply can be set to 1.8V, at which the driver can deliver about 40mW into the 32Ω BTL load.

10.3.4.16 Stereo Class-D Speaker Outputs

The integrated Class-D stereo speaker drivers (SPKLP/SPKLN and SPKRP/SPKRN) are capable of driving two 8Ω differential loads. The speaker drivers can be powered directly from the power supply (2.7V to 5.5V) on the SLVDD and SRVDD terminals, however the voltage (including spike voltage) must be limited below the Absolute Maximum Voltage of 6.0V.

The speaker drivers are capable of supplying 750 mW per channel at 10% THD+N with a 3.6-V power supply and 1.46 W per channel at 10% THD+N with a 5-V power supply. Separate left and right channels can be sent to each Class-D driver through the Lineout signal path, or from the mixer amplifiers in the ADC bypass. If only one speaker is being utilized for playback, the analog mixer before the Left Speaker amplifier can sum the left and right audio signals for monophonic playback.

10.3.5 ADC / Digital Microphone Interface

The TLV320AIC3262 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable oversampling ratio, followed by a digital decimation filter and a programmable miniDSP. The ADC supports sampling rates from 8 kHz to 192 kHz. In order to provide optimal system power management, the stereo recording path can be powered up one channel at a time, to support the case where only mono record capability is required.

The ADC path of the TLV320AIC3262 features a large set of options for signal conditioning as well as signal routing:

  • 2 ADCs
  • 8 analog inputs which can be mixed and/or multiplexed in single-ended and/or differential configuration
  • 2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
  • 2 mixer amplifiers for analog bypass
  • 2 low power analog bypass channels
  • Fine gain adjust of digital channels with 0.1-dB step size
  • Digital volume control with a range of –12 to +20 dB
  • Mute function
  • Automatic gain control (AGC)

In addition to the standard set of ADC features the TLV320AIC3262 also offers the following special functions:

  • Built-in microphone biases
  • Stereo digital microphone interface
    • Allows 2 total microphones
    • Up to 2 digital microphones
    • Up to 2 analog microphones
  • Channel-to-channel phase adjustment
  • Fast charge of ac-coupling capacitors
  • Anti thump
  • Adaptive coefficient update mode

10.3.5.1 ADC Processing Blocks – Overview

The TLV320AIC3262 ADC channel includes a built-in digital decimation filter to process the oversampled data from the sigma-delta modulator to generate digital data at Nyquist sampling rate with high dynamic range. The decimation filter can be chosen from three different types, depending on the required frequency response, group delay, and sampling rate.

10.3.5.1.1 ADC Processing Blocks

The TLV320AIC3262 offers a range of processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users the choice of how much and what type of signal processing they may use and which decimation filter is applied.

The choice between these processing blocks is part of the PowerTune strategy to balance power conservation and signal-processing flexibility. Decreasing the use of signal-processing capabilities reduces the power consumed by the device. Table 11 gives an overview of the available processing blocks of the ADC channel and their properties. The Resource Class Column (RC) gives an approximate indication of power consumption.

The signal processing blocks available is:

  • First-order IIR
  • Scalable number of biquad filters
  • Variable-tap FIR filter
  • AGC

The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low-group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first order IIR, BiQuad and FIR filters have fully user programmable coefficients.

Table 11. ADC Processing Blocks

Processing Blocks Channel Decimation
Filter		 1st Order
IIR Available		 Number
BiQuads		 FIR Required AOSR Value Resource
Class
PRB_R1(1) Stereo A Yes 0 No 128,64,32,16,8,4 7
PRB_R2 Stereo A Yes 5 No 128,64,32,16,8,4 8
PRB_R3 Stereo A Yes 0 25-Tap 128,64,32,16,8,4 8
PRB_R4 Left A Yes 0 No 128,64,32,16,8,4 4
PRB_R5 Left A Yes 5 No 128,64,32,16,8,4 4
PRB_R6 Left A Yes 0 25-Tap 128,64,32,16,8,4 4
PRB_R7 Stereo B Yes 0 No 64,32,16,8,4,2 3
PRB_R8 Stereo B Yes 3 No 64,32,16,8,4,2 4
PRB_R9 Stereo B Yes 0 17-Tap 64,32,16,8,4,2 4
PRB_R10 Left B Yes 0 No 64,32,16,8,4,2 2
PRB_R11 Left B Yes 3 No 64,32,16,8,4,2 2
PRB_R12 Left B Yes 0 17-Tap 64,32,16,8,4,2 2
PRB_R13 Stereo C Yes 0 No 32,16,8,4,2,1 3
PRB_R14 Stereo C Yes 5 No 32,16,8,4,2,1 4
PRB_R15 Stereo C Yes 0 25-Tap 32,16,8,4,2,1 4
PRB_R16 Left C Yes 0 No 32,16,8,4,2,1 2
PRB_R17 Left C Yes 5 No 32,16,8,4,2,1 2
PRB_R18 Left C Yes 0 25-Tap 32,16,8,4,2,1 2
(1) Default

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.6 DAC

The TLV320AIC3262 includes a stereo audio DAC supporting data rates from 8 kHz to 192 kHz. Each channel of the stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a programmable miniDSP, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20kHz. To handle multiple input rates and optimize power dissipation and performance, the TLV320AIC3262 allows the system designer to program the oversampling rates over a wide range from 1 to 1024. The system designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data rates.

The TLV320AIC3262 DAC channel includes a built-in digital interpolation filter to generate oversampled data for the sigma-delta modulator. The interpolation filter can be chosen from three different types depending on required frequency response, group delay and sampling rate.

The DAC path of the TLV320AIC3262 features many options for signal conditioning and signal routing:

  • 2 headphone amplifiers
    • Usable in single-ended stereo or differential mono mode
    • Analog volume setting with a range of -6 to +14 dB
  • 2 line-out amplifiers
    • Usable in single-ended stereo or differential mono mode
  • 2 Class-D speaker amplifiers
    • Usable in stereo differential mode
    • Analog volume control with a settings of +6, +12, +18, +24, and +30 dB
  • 1 Receiver amplifier
    • Usable in mono differential mode
    • Analog volume setting with a range of -6 to +29 dB
  • Digital volume control with a range of -63.5 to +24dB
  • Mute function
  • Dynamic range compression (DRC)

In addition to the standard set of DAC features the TLV320AIC3262 also offers the following special features:

  • Built in sine wave generation (beep generator)
  • Digital auto mute
  • Adaptive coefficient update mode
  • Asynchronous Sample Rate Conversion

10.3.6.1 DAC Processing Blocks — Overview

10.3.6.1.1 DAC Processing Blocks

The TLV320AIC3262 implements signal processing capabilities and interpolation filtering through processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they may use and which interpolation filter is applied.

The choice between these processing blocks is part of the PowerTune strategy balancing power conservation and signal processing flexibility. Less signal processing capability will result in less power consumed by the device. Table 12 gives an overview over all available processing blocks of the DAC channel and their properties. The Resource Class Column (RC) gives an approximate indication of power consumption.

The signal processing blocks available are:

  • First-order IIR
  • Scalable number of biquad filters
  • 3D – Effect
  • Beep Generator

The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first-order IIR and biquad filters have fully user-programmable coefficients.

Table 12. Overview – DAC Predefined Processing Blocks

Processing
Block No.		 Interpolation Filter Channel 1st Order
IIR Available		 Num. of Biquads DRC 3D Beep Generator RC Class
PRB_P1(1) A Stereo No 3 No No No 8
PRB_P2 A Stereo Yes 6 Yes No No 12
PRB_P3 A Stereo Yes 6 No No No 10
PRB_P4 A Left No 3 No No No 4
PRB_P5 A Left Yes 6 Yes No No 6
PRB_P6 A Left Yes 6 No No No 5
PRB_P7 B Stereo Yes 0 No No No 5
PRB_P8 B Stereo No 4 Yes No No 9
PRB_P9 B Stereo No 4 No No No 7
PRB_P10 B Stereo Yes 6 Yes No No 9
PRB_P11 B Stereo Yes 6 No No No 7
PRB_P12 B Left Yes 0 No No No 3
PRB_P13 B Left No 4 Yes No No 4
PRB_P14 B Left No 4 No No No 4
PRB_P15 B Left Yes 6 Yes No No 5
PRB_P16 B Left Yes 6 No No No 4
PRB_P17 C Stereo Yes 0 No No No 3
PRB_P18 C Stereo Yes 4 Yes No No 6
PRB_P19 C Stereo Yes 4 No No No 4
PRB_P20 C Left Yes 0 No No No 2
PRB_P21 C Left Yes 4 Yes No No 3
PRB_P22 C Left Yes 4 No No No 2
PRB_P23 A Stereo No 2 No Yes No 8
PRB_P24 A Stereo Yes 5 Yes Yes No 12
PRB_P25 A Stereo Yes 5 Yes Yes Yes 13
PRB_P26 D Stereo No 0 No No No 1
(1) Default

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.7 Powertune

The TLV320AIC3262 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance, or to an operating point between the two extremes to best fit the application. The TLV320AIC3262 PowerTune modes are called PTM_R1 to PTM_R4 for the recording (ADC) path and PTM_P1 to PTM_P4 for the playback (DAC) path.

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.8 Clock Generation and PLL

To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required internal clock signals at very low power consumption. For cases where such master clocks are not available, the built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL is used to generate some other clock that is only used outside the TLV320AIC3262.

The ADC_CLKIN and DAC_CLKIN can then be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the miniDSP sections.

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.9 Interfaces

10.3.9.1 Control Interfaces

The TLV320AIC3262 control interface supports SPI or I2C communication protocols. For SPI, the SPI_SELECT pin must be tied high; for I2C, SPI_SELECT should be tied low. It is not recommended to change the state of SPI_SELECT during device operation.

10.3.9.1.1 I2C Control

The TLV320AIC3262 supports the I2C control protocol, and will respond by default (GPI3 and GPI4 grounded) to the 7-bit I2C address of 0011000. With the two I2C address terminals, GPI3 and GPI4, the device can be configured to respond to one of four 7-bit I2C addresses, 0011000, 0011001, 0011010, or 0011011. The full 8-bit I2C address can be calculated as:

8-Bit I2C Address = "00110" + GPI4 + GPI3 + R/W

Example: to write to the TLV320AIC3262 with GPI4 = 1 and GPI3 = 0 the 8-Bit I2C Address is "00110" + GPI4 + GPI3 + R/W = "00110100" = 0x34

I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

10.3.9.1.2 SPI Control

In the SPI control mode, the TLV320AIC3262 uses the pins SCL as SS, GPI1 as SCLK, GPO1 as MISO, SDA as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0) and clock phase setting of 1 (typical microprocessor SPI control bit CPHA = 1). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TLV320AIC3262) depend on a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register.

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.9.2 Digital Audio Interfaces

The TLV320AIC3262 features three digital audio data serial interfaces, or audio buses. These three interfaces can be run simultaneously, thereby enabling reception and transmission of digital audio from/to three separate devices. A common example of this scenario would be individual connections to an application processor, a communication baseband processor, and a Bluetooth chipset. By utilizing the TLV320AIC3262 as the center of the audio processing in a portable audio system, mixing of voice and music audio is greatly simplified. In addition, the miniDSP can be utilized to greatly enhance the portable device experience by providing advanced audio processing to both communication and media audio streams simultaneously. In addition to the three simultaneous digital audio interfaces, a fourth set of digital audio terminals can be muxed into Audio Serial Interface 1. In other words, four separate 4-wire digital audio buses can be connected to the TLV320AIC3262, with up to three of these 4-wire buses receiving and sending digital audio data.

TLV320AIC3262 f3262_asi_multi_bus_stereo_channel.gif Figure 29. Typical Multiple Connections to Three Audio Serial Interfaces

Each audio bus on the TLV320AIC3262 is very flexible, including left or right-justified data options, support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master or slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly.

Each of the three audio buses of the TLV320AIC3262 can be configured for left or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies. When configuring an audio interface for six-wire mode, the ADC and DAC paths can operate based on separate word clocks.

The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider. The number of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support the case when multiple TLV320AIC3262s may share the same audio bus. When configuring an audio interface for six-wire mode, the ADC and DAC paths can operate based on separate bit clocks.

The TLV320AIC3262 also includes a feature to offset the position of start of data transfer with respect to the word-clock. This offset can be controlled in terms of number of bit-clocks.

The TLV320AIC3262 also has the feature of inverting the polarity of the bit-clock used for transferring the audio data as compared to the default clock polarity used. This feature can be used independently of the mode of audio interface chosen.

The TLV320AIC3262 further includes programmability to 3-state the DOUT line during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface are put into a 3-state output condition.

By default, when the word-clocks and bit-clocks are generated by the TLV320AIC3262, these clocks are active only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power. However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when word-clock or bit-clocks are used in the system as general-purpose clocks.

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.9.3 miniDSP

10.3.9.3.1 miniDSP

The TLV320AIC3262 features two fully programmable miniDSP cores. The first miniDSP core is tightly coupled to the ADC, the second miniDSP core is tightly coupled to the DAC. The algorithms for the miniDSP must be loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each miniDSP can run up to 1229 instructions on every audio sample at a 48kHz sample rate. The two cores can run fully synchronized and can exchange data. The TLV320AIC3262 features the ability to process a multitude of algorithms simultaneously. For example, the miniDSPs enable noise suppression, sidetone, equalization filtering, dynamic range compression, conversation recording, user-interface sound mixing, and other voice enhancement processing at voice-band sampling rates (such as 8kHz) and high-defintion voice sampling rates (such as 16kHz). The miniDSPs in TLV320AIC3262 also enable advanced DSPsound enhancement algorithms for an enhanced media experience on an audio device.

10.3.9.3.2 Software

Software development for the TLV320AIC3262 is supported through TI's comprehensive PurePath Studio Development Environment. A powerful, easy-to-use tool designed specifically to simplify software development on the TLV320AIC3xxx miniDSP audio platform. The Graphical Development Environment consists of a library of common audio functions that can be dragged-and-dropped into an audio signal flow and graphically connected together. The DSP code can then be assembled from the graphical signal flow with the click of a mouse.

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.9.4 Asynchronous Sample Rate Conversion (ASRC)

For playing back audio or speech signals at various sampling rates, AIC3262 provides an efficient asynchronous sampling rate conversion with the combination of a dedicated ASRC coefficient calculator and the DAC miniDSP engine. The coefficient calculator estimates the audio and speech data input rate versus the DAC playback rate and feeds the calculated coefficients to the miniDSP, with which it converts the audio/speech data to the DAC playback rate. The whole process can be configured automatically without the need of any input sampling rate related information. The input sampling rates as well as the DAC playback rate are not limited to the typical audio/speech sampling rates. A reliable and efficient handshaking is involved between the miniDSP software and the coefficient calculator. For detailed information, please refer to the AIC3262 software programming manual.

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.10 Device Special Functions

The following special functions are available to support advanced system requirements:

  • SAR ADC
  • Headset detection
  • Interrupt generation
  • Flexible pin multiplexing

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.11 Device Power Consumption

Device power consumption largely depends on PowerTune configuration. For information on device power consumption, see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.12 Powertune

The TL320AIC3262 features PowerTune, a mechanism to balance power-versus-performance trade-offs at the time of device configuration. The device can be tuned to minimize power dissipation, to maximize performance, or to an operating point between the two extremes to best fit the application.

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.13 Clock Generation and PLL

To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required internal clock signals at very low power consumption. For cases where such master clocks are not available, the built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL is used to generate some other clock that is only used outside the TLV320AIC3262.

The ADC_CLKIN and DAC_CLKIN can then be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the selectable processing block sections.

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.3.14 Interfaces

10.3.14.1 Control Interfaces

To minimize power consumption, the system ideally provides a master clock that is a suitable integer multiple of the desired sampling frequencies. In such cases, internal dividers can be programmed to set up the required internal clock signals at very low power consumption. For cases where such master clocks are not available, the built-in PLL can be used to generate a clock signal that serves as an internal master clock. In fact, this master clock can also be routed to an output pin and may be used elsewhere in the system. The clock system is flexible enough that it even allows the internal clocks to be derived directly from an external clock source, while the PLL is used to generate some other clock that is only used outside the TLV320AIC3262.

The ADC_CLKIN and DAC_CLKIN can then be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the selectable processing block sections.

10.3.14.2 I2C Control

The TLV320AIC3262 supports the I2C control protocol, and will respond by default (GPI3 and GPI4 grounded) to the 7-bit I2C address of 0011000. With the two I2C address pin, GPI3 and GPI4, the device can be configured to respond to one of four 7-bit I2C addresses, 0011000, 0011001, 0011010, or 0011011. The full 8-bit I2C address can be calculated as:

Equation 2. 8-Bit I2C Address = "00110" + GPI4 + GPI3 + R/W

Example: to write to the TLV320AIC3262 with GPI4 = 1 and GPI3 = 0 the 8-Bit I2C Address is "00110" + GPI4 + GPI3 + R/W = "00110100" = 0x34.

I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.

Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

10.3.14.3 SPI Control

In the SPI control mode, the TLV320AIC3262 uses the pins SCL as SS, GPI1 as SCLK, GPO1 as MISO, SDA as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0) and clock phase setting of 1 (typical microprocessor SPI control bit CPHA = 1). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TLV320AIC3262) depend on a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register.

The TLV320AIC3262 interface is designed so that with a clock-phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SSZ pin can remain low between transmissions; however, the TLV320AIC3262 only interprets the first 8 bits transmitted after the falling edge of SSZ as a command byte, and the next 8 bits as a data byte only if writing to a register. Reserved register bits should be written to their default values. The TLV320AIC3262 is entirely controlled by registers. Reading and writing these registers is accomplished by an 8-bit command sent to the MOSI pin of the part prior to the data for that register. The command is structured as shown in Table 13. The first 7 bits specify the address of the register which is being written or read, from 0 to 127 (decimal). The command word ends with an R/W bit, which specifies the direction of data flow on the serial bus. In the case of a register write, the R/W bit should be set to 0. A second byte of data is sent to the MOSI pin and contains the data to be written to the register. Reading of registers is accomplished in a similar fashion. The 8-bit command word sends the 7-bit register address, followed by the R/W bit = 1 to signify a register read is occurring. The 8- bit register data is then clocked out of the part on the MISO pin during the second 8 SCLK clocks in the frame.

For more details see the TLV320AIC3262 Applications Reference Guide, SLAU309.

TLV320AIC3262 SPI_Timing_Diagram_for_Register_Write_slas679.png Figure 30. SPI Timing Diagram for Register Write
TLV320AIC3262 SPI_Timing_Diagram_for_Register_Read_slas679.png Figure 31. SPI Timing Diagram for Register Read

10.3.14.4 Digital Audio Interfaces

The TLV320AIC3262 features three digital audio data serial interfaces, or audio buses. Any of these digital audio interfaces can be selected for playback and recording through the stereo DACs and stereo ADCs respectively. This enables this audio codec to handle digital audio from different devices on a mobile platform. A common example of this would be individual connections to an application processor, a communication baseband processor, or a Bluetooth chipset. By utilizing the TLV320AIC3262 as the center of the audio processing in a portable audio system, hardware design of the audio system is greatly simplified. In addition to these three individual digital audio interfaces, a fourth set of digital audio pins can be muxed into Audio Serial Interface 1. In other words, four separate 4-wire digital audio buses can be connected to the TLV320AIC3262. However, it should be noted that only one of the three audio serial interfaces can be routed to/from the DACs/ADCs at a time.

Each audio bus on the TLV320AIC3262 is very flexible, including left or right-justified data options, support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master or slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly. Each of the three audio buses of the TLV320AIC3262 can be configured for left or right-justified, I2S, DSP, or TDM modes of operation, where communication with PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies. When configuring an audio interface for six-wire mode, the ADC and DAC paths can operate based on separate word clocks. The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider. The number of bit-clock pulses in a frame may need adjustment to accommodate various word-lengths as well as to support the case when multiple TLV320AIC3262s may share the same audio bus. When configuring an audio interface for six-wire mode, the ADC and DAC paths can operate based on separate bit clocks. The TLV320AIC3262 also includes a feature to offset the position of start of data transfer with respect to the word-clock. This offset can be controlled in terms of number of bit-clocks. The TLV320AIC3262 also has the feature of inverting the polarity of the bit-clock used for transferring the audio data as compared to the default clock polarity used. This feature can be used independently of the mode of audio interface chosen. The TLV320AIC3262 further includes programmability to 3-state the DOUT line during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface are put into a 3-state output condition.

By default, when the word-clocks and bit-clocks are generated by the TLV320AIC3262, these clocks are active only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power. However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when wordclock or bit-clocks are used in the system as general-purpose clocks.

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

TLV320AIC3262 audio_serial_interfaces_slas679.png Figure 32. Typical Multiple Connections to Three Audio Serial Interfaces

10.3.15 miniDSP

The TLV320AIC3262 features two fully programmable miniDSP cores. The first miniDSP core is tightly coupled to the ADC, the second miniDSP core is tightly coupled to the DAC. The algorithms for the miniDSP must be loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each miniDSP can run up to 1145 instructions on every audio sample at a 48kHz sample rate. The two cores can run fully synchronized and can exchange data. The TLV320AIC3262 features the ability to process a multitude of algorithms simultaneously. For example, the miniDSPs enable simultaneous noise suppression, sidetone, equalization filtering, dynamic range compression, conversation recording, user-interface sound mixing, and other voice enhancement processing at voice-band sampling rates (for example 8kHz) and high-defintion voice sampling rates (for example 16kHz). The TLV320AIC3262 miniDSPs also enable advanced DSP sound enhancement algorithms for an enhanced media experience on a portable audio device.

10.3.16 Device Special Functions

The following special functions are available to support advanced system requirements:

  • SAR ADC
  • Headset detection
  • Interrupt generation
  • Flexible pin multiplexing

For more detailed information see the TLV320AIC3262 Applications Reference Guide, SLAU309.

10.4 Device Functional Modes

10.4.1 Recording Mode

The recording mode is activated once the ADC side is enabled. The record path operates from 8kHz mono to 192 kHz stereo recording, and contains programmable input channel configurations supporting single-ended and differential set-ups, as well as floating or mixing input signals. In order to provide optimal system power management, the stereo recording path can be powered up one channel at a time, to support the case where only mono record capability is required. Digital signal processing blocks can remove audible noise that may be introduced by mechanical coupling. The record path can also be configured as a stereo digital microphone PDM interface typically used at 64Fs or 128Fs. The TLV320AIC3262 includes Automatic Gain Control (AGC) for ADC recording.

10.4.2 Playback Mode

Once the DAC side is enabled, the playback mode is activated. The playback path offers signal processing blocks for filtering and effects; headphone, line, receiver, and Class-D speaker outputs; flexible mixing of DAC; and analog input signals as well as programmable volume controls. The playback path contains two high-power headphone output drivers which eliminate the need for ac coupling capacitors. These headphone output drivers can be configured in multiple ways, including stereo and mono BTL. In addition, playback audio can be routed to integrated stereo Class-D speaker drivers or a differential receiver amplifier.

10.4.3 Analog Low Power Bypass Modes

The TLV320AIC3262 is a versatile device designed for ultra low-power applications. In some cases, only a few features of the device are required. For these applications, the unused stages of the device must be powered down to save power and an alternate route should be used. This is called analog low power bypass path. The bypass path modes let the device to save power by turning off unused stages, like ADC, DAC and PGA.

The TLV320AIC3262 offers two analog-bypass modes. In either of the modes, an analog input signal can be routed form an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC resources are required for such operation; this supports low-power operation during analog-bypass mode. In analog low-power bypass mode, line level signals can be routed directly form the analog inputs IN1L to the left lineout amplifier (LOL) and IN1R to LOR. Additionally, line-level signals can be routed directly from these analog inputs to the differential receiver amplifier, which outputs on RECP and RECM.

In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1L to the positive input on differential receiver amplifier (RECP) and IN1R to RECM, with gain control of -78dB to 0dB. This is configured on B0_P1_R38_D[6:0] for the channel and B0_P1_R38_D[6:0] for the left channel and B0_P1_R39_D[6:0] for the right channel.

To use the mixer amplifiers, power them on through B0_P1_R17_D[3:2].

10.5 Register Maps

Table 13. Summary of Register Maps

DECIMAL HEX DESCRIPTION
BOOK NO. PAGE NO. REG NO. BOOK NO. PAGE NO. REG NO.
0 0 0 0x00 0x00 0x00 Page Select Register
0 0 1 0x00 0x00 0x01 Software Reset Register
0 0 2-3 0x00 0x00 0x02-0x03 Reserved Registers
0 0 4 0x00 0x00 0x04 Clock Control Register 1, Clock Input Multiplexers
0 0 5 0x00 0x00 0x05 Clock Control Register 2, PLL Input Multiplexer
0 0 6 0x00 0x00 0x06 Clock Control Register 3, PLL P and R Values
0 0 7 0x00 0x00 0x07 Clock Control Register 4, PLL J Value
0 0 8 0x00 0x00 0x08 Clock Control Register 5, PLL D Values (MSB)
0 0 9 0x00 0x00 0x09 Clock Control Register 6, PLL D Values (LSB)
0 0 10 0x00 0x00 0x0A Clock Control Register 7, PLL_CLKIN Divider
0 0 11 0x00 0x00 0x0B Clock Control Register 8, NDAC Divider Values
0 0 12 0x00 0x00 0x0C Clock Control Register 9, MDAC Divider Values
0 0 13 0x00 0x00 0x0D DAC OSR Control Register 1, MSB Value
0 0 14 0x00 0x00 0x0E DAC OSR Control Register 2, LSB Value
0 0 15-17 0x00 0x00 0x0F-0x11 Reserved Registers
0 0 18 0x00 0x00 0x12 Clock Control Register 10, NADC Values
0 0 19 0x00 0x00 0x13 Clock Control Register 11, MADC Values
0 0 20 0x00 0x00 0x14 ADC Oversampling (AOSR) Register
0 0 21 0x00 0x00 0x15 CLKOUT MUX
0 0 22 0x00 0x00 0x16 Clock Control Register 12, CLKOUT M Divider Value
0 0 23 0x00 0x00 0x17 Timer clock
0 0 24 0x00 0x00 0x18 Low Frequency Clock Generation Control
0 0 25 0x00 0x00 0x19 High Frequency Clock Generation Control 1
0 0 26 0x00 0x00 0x1A High Frequency Clock Generation Control 2
0 0 27 0x00 0x00 0x1B High Frequency Clock Generation Control 3
0 0 28 0x00 0x00 0x1C High Frequency Clock Generation Control 4
0 0 29 0x00 0x00 0x1D High Frequency Clock Trim Control 1
0 0 30 0x00 0x00 0x1E High Frequency Clock Trim Control 2
0 0 31 0x00 0x00 0x1F High Frequency Clock Trim Control 3
0 0 32 0x00 0x00 0x20 High Frequency Clock Trim Control 4
0 0 33-35 0x00 0x00 0x21-0x23 Reserved Registers
0 0 36 0x00 0x00 0x24 ADC Flag Register
0 0 37 0x00 0x00 0x25 DAC Flag Register
0 0 38 0x00 0x00 0x26 DAC Flag Register
0 0 39-41 0x00 0x00 0x27-0x29 Reserved Registers
0 0 42 0x00 0x00 0x2A Sticky Flag Register 1
0 0 43 0x00 0x00 0x2B Interrupt Flag Register 1
0 0 44 0x00 0x00 0x2C Sticky Flag Register 2
0 0 45 0x00 0x00 0x2D Sticky Flag Register 3
0 0 46 0x00 0x00 0x2E Interrupt Flag Register 2
0 0 47 0x00 0x00 0x2F Interrupt Flag Register 3
0 0 48 0x00 0x00 0x30 INT1 Interrupt Control
0 0 49 0x00 0x00 0x31 INT2 Interrupt Control
0 0 50 0x00 0x00 0x32 Reserved Register
0 0 51 0x00 0x00 0x33 Interrupt Format Control Register
0 0 52-59 0x00 0x00 0x34-0x3B Reserved Registers
0 0 60 0x00 0x00 0x3C DAC Processing Block and miniDSP Power Control
0 0 61 0x00 0x00 0x3D ADC Processing Block Control
0 0 62 0x00 0x00 0x3E Reserved Register
0 0 63 0x00 0x00 0x3F Primary DAC Power and Soft-Stepping Control
0 0 64 0x00 0x00 0x40 Primary DAC Master Volume Configuration
0 0 65 0x00 0x00 0x41 Primary DAC Left Volume Control Setting
0 0 66 0x00 0x00 0x42 Primary DAC Right Volume Control Setting
0 0 67 0x00 0x00 0x43 Headset Detection
0 0 68 0x00 0x00 0x44 DRC Control Register 1
0 0 69 0x00 0x00 0x45 DRC Control Register 2
0 0 70 0x00 0x00 0x46 DRC Control Register 3
0 0 71 0x00 0x00 0x47 Beep Generator Register 1
0 0 72 0x00 0x00 0x48 Beep Generator Register 2
0 0 73 0x00 0x00 0x49 Beep Generator Register 3
0 0 74 0x00 0x00 0x4A Beep Generator Register 4
0 0 75 0x00 0x00 0x4B Beep Generator Register 5
0 0 76 0x00 0x00 0x4C Beep Sin(x) MSB
0 0 77 0x00 0x00 0x4D Beep Sin(x) LSB
0 0 78 0x00 0x00 0x4E Beep Cos(x) MSB
0 0 79 0x00 0x00 0x4F Beep Cos(x) LSB
0 0 80 0x00 0x00 0x50 Reserved Register
0 0 81 0x00 0x00 0x51 ADC Channel Power Control
0 0 82 0x00 0x00 0x52 ADC Fine Gain Volume Control
0 0 83 0x00 0x00 0x53 Left ADC Volume Control
0 0 84 0x00 0x00 0x54 Right ADC Volume Control
0 0 85 0x00 0x00 0x55 ADC Phase Control
0 0 86 0x00 0x00 0x56 Left AGC Control 1
0 0 87 0x00 0x00 0x57 Left AGC Control 2
0 0 88 0x00 0x00 0x58 Left AGC Control 3
0 0 89 0x00 0x00 0x59 Left AGC Attack Time
0 0 90 0x00 0x00 0x5A Left AGC Decay Time
0 0 91 0x00 0x00 0x5B Left AGC Noise Debounce
0 0 92 0x00 0x00 0x5C Left AGC Signal Debounce
0 0 93 0x00 0x00 0x5D Left AGC Gain
0 0 94 0x00 0x00 0x5E Right AGC Control 1
0 0 95 0x00 0x00 0x5F Right AGC Control 2
0 0 96 0x00 0x00 0x60 Right AGC Control 3
0 0 97 0x00 0x00 0x61 Right AGC Attack Time
0 0 98 0x00 0x00 0x62 Right AGC Decay Time
0 0 99 0x00 0x00 0x63 Right AGC Noise Debounce
0 0 100 0x00 0x00 0x64 Right AGC Signal Debounce
0 0 101 0x00 0x00 0x65 Right AGC Gain
0 0 102 0x00 0x00 0x66 ADC DC Measurement Control Register 1
0 0 103 0x00 0x00 0x67 ADC DC Measurement Control Register 2
0 0 104 0x00 0x00 0x68 Left Channel DC Measurement Output Register 1 (MSB Byte)
0 0 105 0x00 0x00 0x69 Left Channel DC Measurement Output Register 2 (Middle Byte)
0 0 106 0x00 0x00 0x6A Left Channel DC Measurement Output Register 3 (LSB Byte)
0 0 107 0x00 0x00 0x6B Right Channel DC Measurement Output Register 1 (MSB Byte)
0 0 108 0x00 0x00 0x6C Right Channel DC Measurement Output Register 2 (Middle Byte)
0 0 109 0x00 0x00 0x6D Right Channel DC Measurement Output Register 3 (LSB Byte)
0 0 110-114 0x00 0x00 0x6E-0x72 Reserved Registers
0 0 115 0x00 0x00 0x73 I2C Interface Miscellaneous Control
0 0 116-118 0x00 0x00 0x74-0x76 Reserved Registers
0 0 119 0x00 0x00 0x77 miniDSP Control Register 1, Register Access Control
0 0 120 0x00 0x00 0x78 miniDSP Control Register 2, Register Access Control
0 0 121 0x00 0x00 0x79 miniDSP Control Register 3, Register Access Control
0 0 122-126 0x00 0x00 0x7A-0x7E Reserved Registers
0 0 127 0x00 0x00 0x7F Book Selection Register
0 1 0 0x00 0x01 0x00 Page Select Register
0 1 1 0x00 0x01 0x01 Power Configuration Register
0 1 2 0x00 0x01 0x02 Reserved Register
0 1 3 0x00 0x01 0x03 Left DAC PowerTune Configuration Register
0 1 4 0x00 0x01 0x04 Right DAC PowerTune Configuration Register
0 1 5-7 0x00 0x01 0x05-0x07 Reserved Registers
0 1 8 0x00 0x01 0x08 Common Mode Register
0 1 9 0x00 0x01 0x09 Headphone Output Driver Control
0 1 10 0x00 0x01 0x0A Reserved
0 1 11 0x00 0x01 0x0B Headphone Output Driver De-pop Control
0 1 12 0x00 0x01 0x0C Reserved
0 1 13-16 0x00 0x01 0x0D-0x10 Reserved Registers
0 1 17 0x00 0x01 0x11 Mixer Amplifier Control
0 1 18 0x00 0x01 0x12 Left ADC PGA to Left Mixer Amplifier (MAL) Volume Control
0 1 19 0x00 0x01 0x13 Right ADC PGA to Right Mixer Amplifier (MAR) Volume Control
0 1 20-21 0x00 0x01 0x14-0x15 Reserved Registers
0 1 22 0x00 0x01 0x16 Lineout Amplifier Control 1
0 1 23 0x00 0x01 0x17 Lineout Amplifier Control 2
0 1 24-26 0x00 0x01 0x18-0x1A Reserved
0 1 27 0x00 0x01 0x1B Headphone Amplifier Control 1
0 1 28 0x00 0x01 0x1C Headphone Amplifier Control 2
0 1 29 0x00 0x01 0x1D Headphone Amplifier Control 3
0 1 30 0x00 0x01 0x1E Reserved Register
0 1 31 0x00 0x01 0x1F HPL Driver Volume Control
0 1 32 0x00 0x01 0x20 HPR Driver Volume Control
0 1 33 0x00 0x01 0x21 Charge Pump Control 1
0 1 34 0x00 0x01 0x22 Charge Pump Control 2
0 1 35 0x00 0x01 0x23 Charge Pump Control 3
0 1 36 0x00 0x01 0x24 Reserved Register
0 1 37 0x00 0x01 0x25 Reserved Register
0 1 38 0x00 0x01 0x26 Reserved Register
0 1 39 0x00 0x01 0x27 Reserved Register
0 1 40 0x00 0x01 0x28 Reserved Register
0 1 41 0x00 0x01 0x29 Reserved Register
0 1 42 0x00 0x01 0x2A Reserved
0 1 43-44 0x00 0x01 0x2B-0x2C Reserved Registers
0 1 45 0x00 0x01 0x2D Speaker Amplifier Control 1
0 1 46 0x00 0x01 0x2E Speaker Amplifier Control 2
0 1 47 0x00 0x01 0x2F Speaker Amplifier Control 3
0 1 48 0x00 0x01 0x30 Speaker Amplifier Volume Controls
0 1 49-50 0x00 0x01 0x31-0x32 Reserved Registers
0 1 51 0x00 0x01 0x33 Microphone Bias Control
0 1 52 0x00 0x01 0x34 Input Select 1 for Left Microphone PGA P-Pin
0 1 53 0x00 0x01 0x35 Input Select 2 for Left Microphone PGA P-Pin
0 1 54 0x00 0x01 0x36 Input Select for Left Microphone PGA M-Pin
0 1 55 0x00 0x01 0x37 Input Select 1 for Right Microphone PGA P-Pin
0 1 56 0x00 0x01 0x38 Input Select 2 for Right Microphone PGA P-Pin
0 1 57 0x00 0x01 0x39 Input Select for Right Microphone PGA M-Pin
0 1 58 0x00 0x01 0x3A Input Common Mode Control
0 1 59 0x00 0x01 0x3B Left Microphone PGA Control
0 1 60 0x00 0x01 0x3C Right Microphone PGA Control
0 1 61 0x00 0x01 0x3D ADC PowerTune Configuration Register
0 1 62 0x00 0x01 0x3E ADC Analog PGA Gain Flag Register
0 1 63 0x00 0x01 0x3F DAC Analog Gain Flags Register 1
0 1 64 0x00 0x01 0x40 DAC Analog Gain Flags Register 2
0 1 65 0x00 0x01 0x41 Analog Bypass Gain Flags Register
0 1 66 0x00 0x01 0x42 Driver Power-Up Flags Register
0 1 67-118 0x00 0x01 0x43-0x76 Reserved Registers
0 1 119 0x00 0x01 0x77 Headset Detection Tuning Register 1
0 1 120 0x00 0x01 0x78 Headset Detection Tuning Register 2
0 1 121 0x00 0x01 0x79 Microphone PGA Power-Up Control Register
0 1 122 0x00 0x01 0x7A Reference Powerup Delay Register
0 1 123-127 0x00 0x01 0x7B-0x7F Reserved Registers
0 4 0 0x00 0x04 0x00 Page Select Register
0 4 1 0x00 0x04 0x01 Audio Serial Interface 1, Audio Bus Format Control Register
0 4 2 0x00 0x04 0x02 Audio Serial Interface 1, Left Ch_Offset_1 Control Register
0 4 3 0x00 0x04 0x03 Audio Serial Interface 1, Right Ch_Offset_2 Control Register
0 4 4 0x00 0x04 0x04 Audio Serial Interface 1, Channel Set-up Register
0 4 5 0x00 0x04 0x05 Audio Serial Interface 1, Multi-Channel Set-up Register 1
0 4 6 0x00 0x04 0x06 Audio Serial Interface 1, Multi-Channel Set-up Register 2
0 4 7 0x00 0x04 0x07 Audio Serial Interface 1, ADC Input Control
0 4 8 0x00 0x04 0x08 Audio Serial Interface 1, DAC Output Control
0 4 9 0x00 0x04 0x09 Audio Serial Interface 1, Control Register 9, ADC Slot Tristate Control
0 4 10 0x00 0x04 0x0A Audio Serial Interface 1, WCLK and BCLK Control Register
0 4 11 0x00 0x04 0x0B Audio Serial Interface 1, Bit Clock N Divider Input Control
0 4 12 0x00 0x04 0x0C Audio Serial Interface 1, Bit Clock N Divider
0 4 13 0x00 0x04 0x0D Audio Serial Interface 1, Word Clock N Divider
0 4 14 0x00 0x04 0x0E Audio Serial Interface 1, BCLK and WCLK Output
0 4 15 0x00 0x04 0x0F Audio Serial Interface 1, Data Output
0 4 16 0x00 0x04 0x10 Audio Serial Interface 1, ADC WCLK and BCLK Control
0 4 17 0x00 0x04 0x11 Audio Serial Interface 2, Audio Bus Format Control Register
0 4 18 0x00 0x04 0x12 Audio Serial Interface 2, Data Offset Control Register
0 4 19-22 0x00 0x04 0x13-0x16 Reserved Registers
0 4 23 0x00 0x04 0x17 Audio Serial Interface 2, ADC Input Control
0 4 24 0x00 0x04 0x18 Audio Serial Interface 2, DAC Output Control
0 4 25 0x00 0x04 0x19 Reserved Register
0 4 26 0x00 0x04 0x1A Audio Serial Interface 2, WCLK and BCLK Control Register
0 4 27 0x00 0x04 0x1B Audio Serial Interface 2, Bit Clock N Divider Input Control
0 4 28 0x00 0x04 0x1C Audio Serial Interface 2, Bit Clock N Divider
0 4 29 0x00 0x04 0x1D Audio Serial Interface 2, Word Clock N Divider
0 4 30 0x00 0x04 0x1E Audio Serial Interface 2, BCLK and WCLK Output
0 4 31 0x00 0x04 0x1F Audio Serial Interface 2, Data Output
0 4 32 0x00 0x04 0x20 Audio Serial Interface 2, ADC WCLK and BCLK Control
0 4 33 0x00 0x04 0x21 Reserved
0 4 34 0x00 0x04 0x22 Reserved
0 4 35-38 0x00 0x04 0x23-0x26 Reserved Registers
0 4 39 0x00 0x04 0x27 Reserved Register
0 4 40 0x00 0x04 0x28 Reserved Register
0 4 41 0x00 0x04 0x29 Reserved Register
0 4 42 0x00 0x04 0x2A Reserved Register
0 4 43 0x00 0x04 0x2B Reserved Register
0 4 44 0x00 0x04 0x2C Reserved Register
0 4 45 0x00 0x04 0x2D Reserved Register
0 4 46 0x00 0x04 0x2E Reserved Register
0 4 47 0x00 0x04 0x2F Reserved Register
0 4 48 0x00 0x04 0x30 Reserved Register
0 4 49-64 0x00 0x04 0x31-0x40 Reserved Registers
0 4 65 0x00 0x04 0x41 WCLK1 (Input/Output) Pin Control
0 4 66 0x00 0x04 0x42 Reserved Register
0 4 67 0x00 0x04 0x43 DOUT1 (Output) Pin Control
0 4 68 0x00 0x04 0x44 DIN1 (Input) Pin Control
0 4 69 0x00 0x04 0x45 WCLK2 (Input/Output) Pin Control
0 4 70 0x00 0x04 0x46 BCLK2 (Input/Output) Pin Control
0 4 71 0x00 0x04 0x47 DOUT2 (Output) Pin Control
0 4 72 0x00 0x04 0x48 DIN2 (Input) Pin Control
0 4 73 0x00 0x04 0x49 Reserved Register
0 4 74 0x00 0x04 0x4A Reserved Register
0 4 75 0x00 0x04 0x4B Reserved Register
0 4 76 0x00 0x04 0x4C Reserved Register
0 4 77-81 0x00 0x04 0x4D-0x51 Reserved Registers
0 4 82 0x00 0x04 0x52 MCLK2 (Input) Pin Control
0 4 83-85 0x00 0x04 0x53-0x55 Reserved Registers
0 4 86 0x00 0x04 0x56 GPIO1 (Input/Output) Pin Control
0 4 87 0x00 0x04 0x57 GPIO2 (Input/Output) Pin Control
0 4 88-90 0x00 0x04 0x58-0x5A Reserved Registers
0 4 91 0x00 0x04 0x5B GPI1 (Input) Pin Control
0 4 92 0x00 0x04 0x5C GPI2 (Input) Pin Control
0 4 93-95 0x00 0x04 0x5D-0x5F Reserved Registers
0 4 96 0x00 0x04 0x60 GPO1 (Output) Pin Control
0 4 97-100 0x00 0x04 0x61-0x64 Reserved Registers
0 4 101 0x00 0x04 0x65 Digital Microphone Input Pin Control
0 4 102-117 0x00 0x04 0x66-0x75 Reserved Registers
0 4 118 0x00 0x04 0x76 miniDSP Data Port Control
0 4 119 0x00 0x04 0x77 Digital Audio Engine Synchronization Control
0 4 120-127 0x00 0x04 0x78-0x7F Reserved Registers
20 0 0 0x14 0x00 0x00 Page Select Register
20 0 1-126 0x14 0x00 0x01-0x7E Reserved Registers
20 0 127 0x14 0x00 0x7F Book Selection Register
20 1-26 0 0x14 0x01-0x1A 0x00 Page Select Register
20 1-26 1-7 0x14 0x01-0x1A 0x01-0x07 Reserved Registers
20 1-26 8-127 0x14 0x01-0x1A 0x08-0x7F ADC Fixed Coefficients C(0:767)
40 0 0 0x28 0x00 0x00 Page Select Register
40 0 1 0x28 0x00 0x01 ADC Adaptive CRAM Configuration Register
40 0 2-126 0x28 0x00 0x02-0x7E Reserved Registers
40 0 127 0x28 0x00 0x7F Book Selection Register
40 1-17 0 0x28 0x01-0x11 0x00 Page Select Register
40 1-17 1-7 0x28 0x01-0x11 0x01-0x07 Reserved Registers
40 1-17 8-127 0x28 0x01-0x11 0x08-0x7F ADC Adaptive Coefficients C(0:509)
40 18 0 0x28 0x12 0x00 Page Select Register
40 18 1-7 0x28 0x12 0x01-0x07 Reserved Registers
40 18 8-15 0x28 0x12 0x08-0x0F ADC Adaptive Coefficients C(510:511)
40 18 16-127 0x28 0x12 0x10-0x7F Reserved Registers
60 0 0 0x3C 0x00 0x00 Page Select Register
60 0 1-126 0x3C 0x00 0x01-0x7E Reserved Registers
60 0 127 0x3C 0x00 0x7F Book Selection Register
60 1-35 0 0x3C 0x01-0x23 0x00 Page Select Register
60 1-35 1-7 0x3C 0x01-0x23 0x01-0x07 Reserved Registers
60 1-35 8-127 0x3C 0x01-0x23 0x08-0x7F DAC Fixed Coefficients C(0:1023)
80 0 0 0x50 0x00 0x00 Page Select Register
80 0 1 0x50 0x00 0x01 DAC Adaptive Coefficient Bank number 1 Configuration Register
80 0 2-126 0x50 0x00 0x02-0x7E Reserved Registers
80 0 127 0x50 0x00 0x7F Book Selection Register
80 1-17 0 0x50 0x01-0x11 0x00 Page Select Register
80 1-17 1-7 0x50 0x01-0x11 0x01-0x07 Reserved Registers
80 1-17 8-127 0x50 0x01-0x11 0x08-0x7F DAC Adaptive Coefficient Bank number 1 C(0:509)
80 18 0 0x50 0x12 0x00 Page Select Register
80 18 1-7 0x50 0x12 0x01-0x07 Reserved Registers
80 18 8-15 0x50 0x12 0x08-0x0F DAC Adaptive Coefficient Bank number 1 C(510:511)
80 18 16-127 0x50 0x12 0x10-0x7F Reserved Registers
82 0 0 0x52 0x00 0x00 Page Select Register
82 0 1 0x52 0x00 0x01 DAC Adaptive Coefficient Bank number 2 Configuration Register
82 0 2-126 0x52 0x00 0x02-0x7E Reserved Registers
82 0 127 0x52 0x00 0x7F Book Selection Register
82 1-17 0 0x52 0x01-0x11 0x00 Page Select Register
82 1-17 1-7 0x52 0x01-0x11 0x01-0x07 Reserved Registers
82 1-17 8-127 0x52 0x01-0x11 0x08-0x7F DAC Adaptive Coefficient Bank number 2 C(0:509)
82 18 0 0x52 0x12 0x00 Page Select Register
82 18 1-7 0x52 0x12 0x01-0x07 Reserved Registers
82 18 8-15 0x52 0x12 0x08-0x0F DAC Adaptive Coefficient Bank number 2 C(510:511)
82 18 16-127 0x52 0x12 0x10-0x7F Reserved Registers
100 0 0 0x64 0x00 0x00 Page Select Register
100 0 1-47 0x64 0x00 0x01-0x2F Reserved Registers
100 0 48 0x64 0x00 0x30 ADC miniDSP_A Instruction Control Register 1
100 0 49 0x64 0x00 0x31 ADC miniDSP_A Instruction Control Register 2
100 0 50 0x64 0x00 0x32 ADC miniDSP_A Decimation Ratio Control Register
100 0 51-56 0x64 0x00 0x33-0x38 Reserved Registers
100 0 57 0x64 0x00 0x39 ADC miniDSP_A Instruction Control Register 3
100 0 58 0x64 0x00 0x3A ADC miniDSP_A ISR Interrupt Control
100 0 59-126 0x64 0x00 0x3B-0x7E Reserved Registers
100 0 127 0x64 0x00 0x7F Book Selection Register
100 1-52 0 0x64 0x01-0x34 0x00 Page Select Register
100 1-52 1-7 0x64 0x01-0x34 0x01-0x07 Reserved Registers
100 1-52 8-127 0x64 0x01-0x34 0x08-0x7F miniDSP_A Instructions
120 0 0 0x78 0x00 0x00 Page Select Register
120 0 1-47 0x78 0x00 0x01-0x2F Reserved Registers
120 0 48 0x78 0x00 0x30 DAC miniDSP_D Instruction Control Register 1
120 0 49 0x78 0x00 0x31 DAC miniDSP_D Instruction Control Register 2
120 0 50 0x78 0x00 0x32 DAC miniDSP_D Interpolation Factor Control Register
120 0 51-126 0x78 0x00 0x33-0x7E Reserved Registers
120 0 57 0x78 0x00 0x39 DAC miniDSP_D Instruction Control Register 3
120 0 58 0x78 0x00 0x3A DAC miniDSP_D ISR Interrupt Control
120 0 59-126 0x78 0x00 0x3B-0x7E Reserved Registers
120 0 127 0x78 0x00 0x7F Book Selection Register
120 1-103 0 0x78 0x01-0x67 0x00 Page Select Register
120 1-103 1-7 0x78 0x01-0x67 0x01-0x07 Reserved Registers
120 1-103 8-127 0x78 0x01-0x67 0x08-0x7F miniDSP_D Instructions