9.3.1 Audio Data Converters

The TLV320AIC3106-Q1 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at different sampling rates in various combinations.

The data converters are based on the concept of an f_S(ref) rate that is used internal to the part, and it is related to the actual sampling rates of the converters through a series of ratios. For typical sampling rates, f_S(ref) is either 44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additional restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and also to enable high quality playback of low sampling rate data, without high frequency audible noise being generated.

The sampling rate of the ADC and DAC can be set to f_S(ref) / NDAC or 2 × f_S(ref) / NDAC, with NDAC being 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6.

While only one f_S(ref) can be used at a time in the part, the ADC and DAC sampling rates can differ from each other by using different NADC and NDAC divider ratios for each. For example, with f_S(ref) = 44.1 kHz, the DAC sampling rate can be set to 44.1 kHz by using NDAC = 1, while the ADC sampling rate can be set to 8.018 kHz by using NADC = 5.5.

When the ADCs and DACs are operating at different sampling rates, an additional word clock is required, to provide information regarding where data begins for the ADC versus the DAC. In this case, the standard bit clock signal (which can be supplied through the BCLK pin or through GPIO2) is used to transfer both ADC and DAC data, the standard word clock signal is used to identify the start of the DAC data, and a separate ADC word clock signal (denoted ADWK) is used. This clock can be supplied or generated from GPIO1 at the same time the DAC word clock is supplied or generated from WCLK.

9.3.2 Stereo Audio ADC

The TLV320AIC3106-Q1 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is in operation, the device requires that an audio master clock be provided and appropriate audio clock generation be set up within the device.

To provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to support the case where only mono record capability is required. In addition, both channels can be fully powered or entirely powered down.

The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of 128 f_S to the final output sampling rate of f_S. The decimation filter provides a linear phase output response with a group delay of 17 / f_S. The –3-dB bandwidth of the decimation filter extends to 0.45 f_S and scales with the sample rate (f_S). The filter has minimum 75-dB attenuation over the stop band from 0.55 f_S to 64 f_S. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency that can be independently set.

Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for analog antialiasing filtering are very relaxed. The TLV320AIC3106-Q1 integrates a second-order analog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter, provides sufficient antialiasing filtering without requiring additional external components.

The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on the register programming (see Page 0, Registers 19 and 22). This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC power-down flag is no longer set, the audio master clock can be shut down.

9.3.2.1 Stereo Audio ADC High-Pass Filter

Often in audio applications it is desirable to remove the DC offset from the converted audio data stream. The TLV320AIC3106-Q1 has a programmable first-order high-pass filter which can be used for this purpose. The digital filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients, N0, N1, and D1. The transfer function of the digital high-pass filter is of the form:

Equation 1.

Programming the left channel is done by writing to Page 1, Registers 65 to 70, and the right channel is programmed by writing to Page 1, Registers 71 to 76. After the coefficients have been loaded, these ADC high-pass filter coefficients can be selected by writing to Page 0, Register 107, Bits D7 to D6, and the high-pass filter can be enabled by writing to Page 0, Register 12, Bits D7 to D4.

9.3.3 Automatic Gain Control (AGC)

An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant output signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum PGA gain applicable that allow the algorithm to be fine tuned for any particular application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal.

Completely independent AGC circuitry is included with each ADC channel with entirely independent control over the algorithm from one channel to the next. This is attractive in cases where two microphones are used in a system, but may have different placement in the end equipment and require different dynamic performance for optimal system operation.

Target level represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The TLV320AIC3106-Q1 allows programming of eight different target levels, which can be programmed from –5.5 dB to –24 dB relative to a full-scale signal. Because the device reacts to the signal absolute average and not to peak levels, TI recommends the target level be set with enough margin to avoid clipping at the occurrence of loud sounds.

Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It can be varied from 7 ms to 1,408 ms. The extended Right Channel Attack time can be programmed by writing to Page 0, Register 103, and Left Channel is programmed by writing to Page 0, Register 105.

Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied in the range from 0.05 s to 22.4 s. The extended Right Channel Decay time can be programmed by writing to Page 0, Register 104, and Left Channel is programmed by writing to Page 0, Register 106.

The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the clock set up that is used. The table below shows the relationship of the NADC ratio to the maximum time available for the AGC decay. In practice, these maximum times are extremely long for audio applications and must not limit any practical AGC decay time that is required by the system.

Noise gate threshold determines the level below which if the input speech average value falls, AGC considers it as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every FS and sets the noise threshold flag. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold setting. This ensures that noise does not get gained up in the absence of speech. Noise threshold level in the AGC algorithm is programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also available. This operation includes programmable debounce and hysteresis functionality to avoid the AGC gain from cycling between high gain and 0 dB when signals are near the noise threshold level. When the noise threshold flag is set, the status of gain applied by the AGC and the saturation flag may be ignored.

Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.

Figure 13. Typical Operation Of The AGC Algorithm During Speech Recording

The time constants here are correct when the ADC is not in double-rate audio mode. The time constants are achieved using the f_S(ref) value programmed in the control registers. However, if the f_S(ref) is set in the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different f_S(ref) in practice, then the time constants would not be correct.

The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the clock set up that is used. Table 1 shows the relationship of the NADC ratio to the maximum time available for the AGC decay. In practice, these maximum times are extremely long for audio applications and must not limit any practical AGC decay time that is required by the system.

9.3.4 Stereo Audio DAC

The TLV320AIC3106-Q1 includes a stereo audio DAC supporting sampling rates from 8 kHz to 96 kHz. Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, multi-bit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 × f_S(ref) and changing the oversampling ratio as the input sample rate is changed. For an f_S(ref) of 48 kHz, the digital delta-sigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly, for an f_S(ref) rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.

The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is enabled in the DAC.

• Allowed Q values = 4, 8, 9, 12, 16
• Q values where equivalent f_S(ref) can be achieved by turning on PLL
• Q = 5, 6, 7 (set P = 5, 6, 7 and K = 16 and PLL enabled)
• Q = 10, 14 (set P = 5, 7 and K = 8 and PLL enabled)

9.3.5 Digital Audio Processing For Playback

The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3D effects processing. The de-emphasis function is implemented by a programmable digital filter block with fully programmable coefficients (see Page 1, Registers 21 to 26 for left channel, Page 1, Registers 47 to 52 for right channel). If de-emphasis is not required in a particular application, this programmable filter block can be used for some other purpose. The de-emphasis filter transfer function is given by:

Equation 2.

where the N0, N1, and D1 coefficients are fully programmable individually for each channel. The coefficients that must be loaded to implement standard de-emphasis filters are given in Table 2.

In addition to the de-emphasis filter block, the DAC digital effects processing includes a fourth-order digital IIR filter with programmable coefficients (one set per channel). This filter is implemented as cascade of two biquad sections with frequency response given by:

Equation 3.

The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed. The structure of the filtering when configured for independent channel processing is shown in Figure 14, with LB1 corresponding to the first left-channel biquad filter using coefficients N0, N1, N2, D1, and D2. LB2 similarly corresponds to the second left-channel biquad filter using coefficients N3, N4, N5, D4, and D5. The RB1 and RB2 filters refer to the first and second right-channel biquad filters, respectively.

Figure 14. Structure Of The Digital Effects Processing For Independent Channel Processing

The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most commonly used in portable audio applications. The default N and D coefficients in the part are given in Table 3 and implement a shelving filter with 0-dB gain from DC to approximately 150 Hz, at which point it rolls off to a 3‑dB attenuation for higher frequency signals, thus giving a 3‑dB boost to signals below 150 Hz. The N and D coefficients are represented by 16-bit, 2s-complement numbers with values ranging from –32768 to 32767.

The digital processing also includes capability to implement 3D processing algorithms by providing means to process the mono mix of the stereo input, and then combine this with the individual channel signals for stereo output playback. The architecture of this processing mode, and the programmable filters available for use in the system, is shown in Figure 15. The programmable attenuation block provides a method of adjusting the level of 3D effect introduced into the final stereo output. This combined with the fully programmable biquad filters in the system enables the user to fully optimize the audio effects for a particular system and provide extensive differentiation from other systems using the same device.

Figure 15. Architecture Of The Digital Audio Processing When 3D Effects Are Enabled

TI recommends the digital effects filters be disabled while the filter coefficients are being modified. While new coefficients are being written to the device over the control port, it is possible that a filter using partially updated coefficients may actually implement an unstable system and lead to oscillation or objectionable audio output. By disabling the filters, changing the coefficients, and then re-enabling the filters, these types of effects can be entirely avoided.

9.3.6 Digital Interpolation Filter

The digital interpolation filter upsamples the output of the digital audio processing block by the required oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter stages. The filter provides a linear phase output with a group delay of 21 / f_S. In addition, programmable digital interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at multiples of 8-kHz (8 kHz, 16 kHz, 24 kHz, and so on). The images at 8 kHz and 16 kHz are below 20 kHz and still audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The interpolation filter is designed to maintain at least 65-dB rejection of images that land below 7.455 f_S. To use the programmable interpolation capability, the f_S(ref) must be programmed to a higher rate (restricted to be in the range of 39 kHz to 53 kHz when the PLL is in use), and the actual f_S is set using the NDAC divider. For example, if f_S = 8 kHz is required, then f_S(ref) can be set to 48 kHz, and the DAC f_S set to f_S(ref) / 6. This ensures that all images of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency range.

9.3.7 Delta-Sigma Audio Dac

The stereo audio DAC incorporates a third-order multi-bit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques. The analog reconstruction filter design consists of a 6-tap analog FIR filter followed by a continuous time RC filter. The analog FIR operates at a rate of 128 × f_S(ref) (6.144 MHz when f_S(ref) = 48 kHz, 5.6448 MHz when f_S(ref) = 44.1 kHz). The DAC analog performance may be degraded by excessive clock jitter on the MCLK input. Therefore, take care to keep jitter on this clock to a minimum.

9.3.8 Audio Dac Digital Volume Control

The audio DAC includes a digital volume control block which implements a programmable digital gain. The volume level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, in addition to a mute bit, independently for each channel. The volume level of both channels can also be changed simultaneously by the master volume control. Gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by one step per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be slowed to one step per two input samples through a register bit.

Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be important if the host wishes to mute the DAC before making a significant change, such as changing sample rates. To help with this situation, the device provides a flag back to the host through a read-only register bit that alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired volume level. The soft-stepping feature can be disabled through register programming. If soft-stepping is enabled, the MCLK signal must be kept applied to the device until the DAC power-down flag is set. When this flag is set, the internal soft-stepping process and power down sequence is complete, and the MCLK can then be stopped if desired.

The TLV320AIC3106-Q1 also includes functionality to detect when the user switches on or off the de-emphasis or digital audio processing functions, to first (1) soft-mute the DAC volume control, (2) change the operation of the digital effects processing, and (3) soft-unmute the part. This avoids any possible pops or clicks in the audio output due to instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the DAC. The circuit begins operation at power up with the volume control muted, then soft-steps it up to the desired volume level. At power down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.

9.3.9 Analog Output Common-Mode Adjustment

The output common-mode voltage and output range of the analog output are determined by an internal bandgap reference, in contrast to other codecs that may use a divided version of the supply. This scheme is used to reduce the coupling of noise that may be on the supply into the audio signal path.

However, due to the possible wide variation in analog supply range (2.7 V to 3.6 V), an output common-mode voltage setting of 1.35 V, which would be used for a 2.7-V supply case, is overly conservative if the supply is actually much larger, such as 3.3 V or 3.6 V. To optimize device operation, the TLV320AIC3106-Q1 includes a programmable output common-mode level, which can be set by register programming to a level most appropriate to the actual supply range used by a particular customer. The output common-mode level can be varied among four different values, ranging from 1.35 V (most appropriate for low supply ranges, near 2.7 V) to 1.8 V (most appropriate for high supply ranges, near 3.6 V). There is also some limitation on the range of DVDD voltage as well in determining which setting is most appropriate.

9.3.10 Audio DAC Power Control

The stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC channel can be powered up or down independently. This provides power savings when only a mono playback stream is required.

9.3.11 Audio Analog Inputs

The TLV320AIC3106-Q1 includes ten analog audio input pins, which can be configured as up to four fully-differential pair plus one single-ended pair of audio inputs, or up to six single-ended audio inputs. These pins connect through series resistors and switches to the virtual ground terminals of two fully differential opamps (one per ADC PGA channel). By selecting to turn on only one set of switches per opamp at a time, the inputs can be effectively muxed to each ADC PGA channel.

By selecting to turn on multiple sets of switches per opamp at a time, mixing can also be achieved. Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal opamps, resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented, the user must take adequate precautions to avoid such a saturation case from occurring. In general, the mixed signal must not exceed 2 V_PP (single-ended) or 4 V_PP (differential).

In most mixing applications, the levels of the individual signals being mixed must be adjusted. For example, if a soft signal and a large signal are to be mixed and played together, the soft signal generally must be amplified to a level comparable to the large signal before mixing. To accommodate this, the TLV320AIC3106-Q1 includes input level control on each of the individual inputs before they are mixed or muxed into the ADC PGAs, with gain programmable from 0 dB to –12 dB in 1.5-dB steps. This input level control is not intended to be a volume control, but instead used occasionally for level setting. Soft-stepping of the input level control settings is implemented in this device, with the speed and functionality following the settings used by the ADC PGA for soft-stepping.

The TLV320AIC3106-Q1 supports the ability to mix up to three fully-differential analog inputs into each ADC PGA channel. Figure 16 shows the mixing configuration for the left channel, which can mix the signals LINE1LP-LINE1LM, LINE2LP-LINE2LM, and LINE1RP-LINE1RM

Figure 16. Left Channel Fully-Differential Analog Input Mixing Configuration

Three fully-differential analog inputs can similarly be mixed into the right ADC PGA as well, consisting of LINE1RP-LINE1RM, LINE2RP-LINE2RM, and LINE1LP-LINE1LM. It is not necessary to mix all three fully-differential signals if this is not desired, unnecessary inputs can simply be muted using the input level control registers.

Inputs can also be selected as single-ended instead of fully-differential, and mixing or muxing into the ADC PGAs is also possible in this mode. It is not possible, however, for an input pair to be selected as fully-differential for connection to one ADC PGA and simultaneously selected as single-ended for connection to the other ADC PGA channel. However, it is possible for an input to be selected or mixed into both left and right channel PGAs, as long as it has the same configuration for both channels (either both single-ended or both fully-differential).

Figure 17 shows the single-ended mixing configuration for the left channel ADC PGA, which enables mixing of the signals LINE1LP, LINE2LP, LINE1RP, MIC3L, and MIC3R. The right channel ADC PGA mix is similar, enabling mixing of the signals LINE1RP, LINE2RP, LINE1LP, MIC3L, and MIC3R.

Figure 17. Left Channel Single-Ended Analog Input Mixing Configuration

9.3.12 Analog Input Bypass Path Functionality

The TLV320AIC3106-Q1 includes the additional ability to route some analog input signals past the integrated data converters, for mixing with other analog signals and then direct connection to the output drivers. The TLV320AIC3106-Q1 supports this in a low power mode by providing a direct analog path through the device to the output drivers, while all ADCs and DACs can be completely powered down to save power.

For fully-differential inputs, the TLV320AIC3106-Q1 provides the ability to pass the signals LINE2LP-LINE2LM and LINE2RP-LINE2RM to the output stage directly. If in single-ended configuration, the device can pass the signal LINE2LP and LINE2RP to the output stage directly.

9.3.13 ADC PGA Signal Bypass Path Functionality

In addition to the input bypass path described in Analog Input Bypass Path Functionality, the TLV320AIC3106‑Q1 also includes the ability to route the ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connection to the output drivers. These bypass functions are described in more detail in the sections on output mixing and output driver configurations.

9.3.14 Input Impedance and VCM Control

The TLV320AIC3106-Q1 includes several programmable settings to control analog input pins, particularly when they are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a 3-state condition, such that the input impedance seen looking into the device is extremely high. The pins on the device do include protection diode circuits connected to AVDD and AVSS. Thus, if any voltage is driven onto a pin approximately one diode drop (approximately 0.6 V) above AVDD or one diode drop below AVSS, these protection diodes begins conducting current, resulting in an effective impedance that no longer appears as a 3-state condition.

Another programmable option for unselected analog inputs is to weakly hold them at the common-mode input voltage of the ADC PGA (which is determined by an internal bandgap voltage reference). This is useful to keep the AC-coupling capacitors connected to analog inputs biased up at a normal DC level, thus avoiding the necessity of charging them up suddenly when the input is changed from being unselected to selected for connection to an ADC PGA. This option is controlled in Page 0, Registers 20 and 23. The user must ensure this option is disabled when an input is selected for connection to an ADC PGA or selected for the analog input bypass path, because it can corrupt the recorded input signal if left operational when an input is selected.

In most cases, the analog input pins on the TLV320AIC3106-Q1 must be AC-coupled to analog input sources, the only exception to this generally being if an ADC is being used for DC voltage measurement. The AC-coupling capacitor causes a highpass filter pole to be inserted into the analog signal path, so the size of the capacitor must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies with the setting of the input level control, starting at approximately 20 kΩ with an input level control setting of 0 dB, and increasing to approximately 80 kΩ when the input level control is set at –12 dB. For example, using a 0.1-μF AC-coupling capacitor at an analog input results in a highpass filter pole of 80 Hz when the 0-dB input level control setting is selected.

9.3.15 MICBIAS Generation

The TLV320AIC3106-Q1 includes a programmable microphone bias output voltage (MICBIAS), capable of providing output voltages of 2 V or 2.5 V (both derived from the on-chip bandgap voltage) with 4-mA output current drive. In addition, the MICBIAS may be programmed to be switched to AVDD directly through an on-chip switch, or it can be powered down completely when not required, for power savings. This function is controlled by register programming in Page 0, Register 25.

9.3.16 Analog Fully Differential Line Output Drivers

The TLV320AIC3106-Q1 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load. The output stage design leading to the fully differential line output drivers is shown in Figure 18 and Figure 19. This design includes extensive capability to adjust signal levels independently before any mixing occurs, beyond that already provided by the PGA gain and the DAC digital volume control.

The LINE2L/R signals refer to the signals that travel through the analog input bypass path to the output stage. The PGA_L/R signals refer to the outputs of the ADC PGA stages that are similarly passed around the ADC to the output stage. Because both left and right channel signals are routed to all output drivers, a mono mix of any of the stereo signals can easily be obtained by setting the volume controls of both left and right channel signals to –6 dB and mixing them. Undesired signals can also be disconnected from the mix as well through register control.

Figure 18. Architecture Of The Output Stage Leading To The Fully Differential Line Output Drivers

Figure 19. Detail Of The Volume Control and Mixing Function

The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control based on the requirements of the system. If mixing of the DAC audio with other signals is not required, and the DAC output is only required at the stereo line outputs, then TI recommends to use the routing through path DAC_L3/R3 to the fully differential stereo line outputs. This results not only in higher quality output performance, but also in lower power operation, because the analog volume controls and mixing blocks ahead of these drivers can be powered down.

If instead the DAC analog output must be routed to multiple output drivers simultaneously (such as to LEFT_LOP/M, RIGHT_LOP/M, and MONO_LOP/M) or must be mixed with other analog signals, then the DAC outputs must be switched through the DAC_L1/R1 path. This option provides the maximum flexibility for routing of the DAC analog signals to the output drivers

The TLV320AIC3106-Q1 includes an output level control on each output driver with limited gain adjustment from 0 dB to 9 dB. The output driver circuitry in this device are designed to provide a low distortion output while playing fullscale stereo DAC signals at a 0-dB gain setting. However, a higher amplitude output can be obtained at the cost of increased signal distortion at the output. This output level control allows the user to make this tradeoff based on the requirements of the end equipment. This output level control is not intended to be used as a standard output volume control. It is expected to be used only sparingly for level setting, such as adjustment of the fullscale output range of the device.

Each differential line output driver can be powered down independently of the others when it is not required in the system. When placed into powerdown through register programming, the driver output pins are placed into a 3‑stated, high-impedance state.

9.3.17 Analog High Power Output Drivers

The TLV320AIC3106-Q1 includes four high power output drivers with extensive flexibility in their usage. These output drivers are individually capable of driving 30 mW each into a 16-Ω load in single-ended configuration, and they can be used in pairs connected in bridge-terminated load (BTL) configuration between two driver outputs.

The high power output drivers can be configured in a variety of ways, including:

1. driving up to two fully differential output signals
2. driving up to four single-ended output signals
3. driving two single-ended output signals, with one or two of the remaining drivers driving a fixed VCM level, for a pseudo-differential stereo output

The output stage architecture leading to the high power output drivers is shown in Figure 20, with the volume control and mixing blocks being effectively identical to that shown in Figure 19. Each of these drivers have a output level control block like those included with the line output drivers, allowing gain adjustment up to 9 dB on the output signal. As in the previous case, this output level adjustment is not intended to be used as a standard volume control, but instead is included for additional fullscale output signal level control.

Two of the output drivers, HPROUT and HPLOUT, include a direct connection path for the stereo DAC outputs to be passed directly to the output drivers and bypass the analog volume controls and mixing networks, using the DAC_L2/R2 path. As in the line output case, this functionality provides the highest quality DAC playback performance with reduced power dissipation, but can only be used if the DAC output is not routed to multiple output drivers simultaneously, and if mixing of the DAC output with other analog signals is not required.

Figure 20. Architecture Of The Output Stage Leading To The High Power Output Drivers

The high power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions. The user must first program the type of output configuration being used in Page 0, Register 14, to allow the device to select the optimal power-up scheme to avoid output artifacts. The power-up delay time for the high power output drivers is also programmable over a wide range of time delays, from instantaneous up to 4 s, using Page 0, Register 42.

When these output drivers are powered down, they can be placed into a variety of output conditions based on register programming. If lowest power operation is desired, then the outputs can be placed into a 3-state condition, and all power to the output stage is removed. However, this generally results in the output nodes drifting to rest near the upper or lower analog supply, due to small leakage currents at the pins. This then results in a longer delay requirement to avoid output artifacts during driver power-on. To reduce this required power-on delay, the TLV320AIC3106-Q1 includes an option for the output pins of the drivers to be weakly driven to the VCM level they would normally rest at when powered with no signal applied. This output VCM level is determined by an internal bandgap voltage reference, and thus results in extra power dissipation when the drivers are in powerdown. However, this option provides the fastest method for transitioning the drivers from powerdown to full power operation without any output artifact introduced.

The device includes a further option that falls between the other two, while it requires less power drawn while the output drivers are in powerdown, it also takes a slightly longer delay to power-up without artifact than if the bandgap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly driven to a voltage of approximately half the DRVDD1/2 supply level using an internal voltage divider. This voltage does not match the actual VCM of a fully powered driver, but due to the output voltage being close to its final value, a much shorter power-up delay time setting can be used and still avoid any audible output artifacts. These output voltage options are controlled in Page 0, Register 42.

The high power output drivers can also be programmed to power up first with the output level control in a highly attenuated state, then the output driver automatically slowly reduces the output attenuation to reach the desired output level setting programmed. This capability is enabled by default but can be enabled in Page 0, Register 40.

9.3.18 Short Circuit Output Protection

The TLV320AIC3106-Q1 includes programmable short-circuit protection for the high power output drivers, for maximum flexibility in a given application. By default, if these output drivers are shorted, they automatically limit the maximum amount of current that can be sourced to or sunk from a load, thereby protecting the device from an overcurrent condition. In this mode, the user can read Page 0, Register 95 to determine whether the part is in short-circuit protection or not, and then decide whether to program the device to power down the output drivers. However, the device includes further capability to automatically power down an output driver whenever it does into short-circuit protection, without requiring intervention from the user. In this case, the output driver stays in a power down condition until the user specifically programs it to power down and then power back up again, to clear the short-circuit flag.

9.3.19 Jack and Headset Detection

The TLV320AIC3106-Q1 includes extensive capability to monitor a headphone, microphone, or headset jack, determine if a plug has been inserted into the jack, and then determine what type of headset or headphone is wired to the plug. Figure 21 shows one configuration of the device that enables detection and determination of headset type when a pseudo-differential (capless) stereo headphone output configuration is used. The registers used for this function are Page 0, Registers 14, 96, 97, and 13. The type of headset detected can be read back from Page 0, Register 13. For best results, TI recommends selecting a MICBIAS value as high as possible, and to program the output driver common-mode level at a 1.35-V or 1.5-V level.

Figure 21. Configuration Of Device For Jack Detection Using A Pseudo-Differential (Capless) Headphone Output Connection

A modified output configuration used when the output drivers are AC-coupled is shown in Figure 22. In this mode, the device cannot accurately determine if the inserted headphone is a mono or stereo headphone.

Figure 22. Configuration Of Device For Jack Detection Using An AC-Coupled Stereo Headphone Output Connection

An output configuration for the case of the outputs driving fully differential stereo headphones is shown in Figure 23. In this mode, there is a requirement on the jack side that either HPLCOM or HPLOUT get shorted to ground if the plug is removed, which can be implemented using a spring terminal in a jack. For this mode to function properly, short-circuit detection must be enabled and configured to power down the drivers if a short-circuit is detected. The registers that control this functionality are in Page 0, Register 38, Bits D2 to D1.

Figure 23. Configuration Of Device For Jack Detection Using A Fully Differential Stereo Headphone Output Connection

9.3.20 General-Purpose I/O

TLV320AIC3106-Q1 has two dedicated pins for general-purpose I/O. These pins can be used to read status of external signals through register read when configured as general-purpose input. When configured as general-purpose output , these pins can also drive logic high or low. Besides these standard GPIO functions, these pins can also be used in a variety of ways, such as output for internal clocks and interrupt signals. The TLV320AIC3106-Q1 generates a variety of interrupts of use to the host processor such interrupts on jack detection, button press, short-circuit detection, and AGC noise detection. All these interrupts can be routed individually to the GPIO pins or can be combined by a logical OR. In case of a combined interrupt, the user can read an internal status register to find the actual cause of interrupt. When configured as interrupt, the TLV320AIC3106-Q1 also offers the flexibility of generating a single pulse or a train of pulses until the interrupt status register is read by the user.

9.4.1 Digital Audio Processing For Record Path

In applications where record only is selected, and DAC is powered down, the playback path signal processing blocks can be used in the ADC record path. These filtering blocks can support high pass, low pass, band pass or notch filtering. In this mode, the record only path has switches SW-D1 through SW-D4 closed, and reroutes the ADC output data through the digital signal processing blocks. Because the DAC's Digital Signal Processing blocks are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC digital processing and are located on Page 1, Registers 1 to 52. This record only mode is enabled by powering down both DACs by writing to Page 0, Register 37, Bits D7 to D6 (D7 = D6 = 0). Next, enable the digital filter pathway for the ADC by writing a 1 to Page 0, Register 107, Bit D3. This pathway is only enabled if both DACs are powered down. This record only path can be seen in Figure 24.

Figure 24. Record Only Mode With Digital Processing Path Enabled

9.4.2 Increasing DAC Dynamic Range

The TLV320AIC3106-Q1 allows trading off dynamic range with power consumption. The DAC dynamic range can be increased by writing to Page 0, Register 109, Bits D7 to D6. The lowest DAC current setting is the default, and the dynamic range is displayed in the datasheet table. Increasing the current can increase the DAC dynamic range by up to 1.5 dB.

9.4.3 Passive Analog Bypass During Powerdown

Programming the TLV320AIC3106-Q1 to passive analog bypass occurs by configuring the output stage switches for pass through. This is done by opening switches SW-L0, SW-L3, SW-R0, SW-R3 and closing either SW-L1 or SW-L2 and SW-R1 or SW-R2. See Figure 25 Passive Analog Bypass Mode Configuration. Programming this mode is done by writing to Page 0, Register 108.

Connecting MIC1LP/LINE1LP input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SW-L0, this action is done by writing a 1 to Page 0, Register 108, Bit D0. Connecting MIC2LP/LINE2LP input signal to the LEFT_LOP pin is done by closing SW-L2 and opening SW-L0, this action is done by writing a 1 to Page 0, Register 108, Bit D2. Connecting MIC1LM/LINE1LM input signal to the LEFT_LOM pin is done by closing SW-L4 and opening SW-L3, this action is done by writing a 1 to Page 0, Register 108, Bit D1. Connecting MIC2LM/LINE2LM input signal to the LEFT_LOM pin is done by closing SW-L5 and opening SW-L3, this action is done by writing a 1 to Page 0, Register 108, Bit D3.

Connecting MIC1RP/LINE1RP input signal to the RIGHT_LOP pin is done by closing SW-R1 and opening SW-R0, this action is done by writing a 1 to Page 0, Register 108, Bit D4. Connecting MIC2RP/LINE2RP input signal to the RIGHT_LOP pin is done by closing SW-R2 and opening SW-R0, this action is done by writing a 1 to Page 0, Register 108, Bit D6. Connecting MIC1RM/LINE1RM input signal to the RIGHT_LOM pin is done by closing SW-R4 and opening SW-R3, this action is done by writing a 1 to Page 0, Register 108, Bit D5. Connecting MIC2RM/LINE2RM input signal to the RIGHT_LOM pin is done by closing SW-R5 and opening SW-R3, this action is done by writing a 1 to Page 0, Register 108, Bit D7. A diagram of the passive analog bypass mode configuration can be seen in Figure 25.

In general, connecting two switches to the same output pin must be avoided, as this error shorts two input signals together, and causes distortion of the signal as the two signal are in contention, and poor frequency response would also likely occur.

Figure 25. Passive Analog Bypass Mode Configuration

9.4.4 Digital Microphone Connectivity

The TLV320AIC3106-Q1 includes support for connection of a digital microphone to the device by routing the digital signal directly into the ADC digital decimation filter, where it is filtered, downsampled, and provided to the host processor over the audio data serial bus.

When digital microphone mode is enabled, the TLV320AIC3106-Q1 provides an oversampling clock output for use by the digital microphone to transmit its data. The TLV320AIC3106-Q1 includes the capability to latch the data on either the rising, falling, or both edges of this supplied clock, enabling support for stereo digital microphones.

In this mode, the oversampling ratio of the digital mic modulator can be programmed as 128, 64 or 32 times the ADC sample rate, ADCFS. The GPIO1 pin outputs the serial oversampling clock at the programmed rate. TLV320AIC3106-Q1 latches the data input on GPIO2 as the Left and Right channel digital microphone data. For the Left channel input, GPIO2 is sampled on the rising edge of the clock, and for the Right channel input, GPIO2 is sampled on the falling edge of the clock. If a single digital mic channel is required then the corresponding ADC channel must be powered up, and the unused channel must be powered down. When digital microphone mode is enabled, neither ADC can be used for digitizing analog inputs.

Configuring the digital microphone configuration set up is done by writing to Page 0, Register 107, Bits D5 to D4, and Register 25, Bits D5 to D4.

9.5.1 Hardware Reset

The TLV320AIC3106-Q1 requires a hardware reset after power-up for proper operation. After all power supplies are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not performed, the TLV320AIC3106-Q1 may not respond properly to register reads and writes.

9.5.2 Digital Control Serial Interface

The TLV320AIC3106-Q1 control interface supports SPI or I²C communication protocols, with the protocol selectable using the SELECT pin. For SPI, SELECT must be tied high; for I²C, SELECT must be tied low. The state of SELECT must not be changed during device operation.

9.5.2.1 SPI Control Mode

Figure 26. SPI Write

Figure 27. SPI Read

In the SPI control mode, the TLV320AIC3106-Q1 uses the pins MFP0 = SSB, MFP1 = SCLK, MFP2 = MISO, MFP3 = MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication from a host processor (the master) to peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TLV320AIC3106-Q1) depend on a master to start and synchronize transmissions.

A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register.

The TLV320AIC3106-Q1 interface is designed so that with a clock phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on the first serial clock edge. The SSB pin can remain low between transmissions; however, the TLV320AIC3106‑Q1 only interprets the first 8 bits transmitted after the falling edge of SSB as a command byte, and the next 8 bits as a data byte only if writing to a register. Reserved register bits must be written to their default values.

9.5.3 I²C Control Mode

The TLV320AIC3106-Q1 supports the I²C control protocol when the SELECT pin is tied low, using 7-bit addressing and capable of both standard and fast modes. For I²C fast mode, note that the minimum timing for each of tHD‑STA, tSU-STA, and tSU-STO is 0.9 µs, as seen in Figure 28. When in I²C control mode, the TLV320AIC3106-Q1 can be configured for one of four different addresses, using the multifunction pins MFP0 and MFP1, which control the two LSBs of the device address. The 5 MSBs of the device address are fixed as 00110 and cannot be changed, while the two LSBs are given by MFP1:MFP0. This results in four possible device addresses:

Figure 28. I²C Interface Timing

I²C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I²C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Communication on the I²C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I²C devices can act as masters or slaves, but the TLV320AIC3106-Q1 can only act as a slave device.

An I²C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted across the I²C bus in groups of eight bits. To send a bit on the I²C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the receivers shift register.

The I²C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. Under normal circumstances the master drives the clock line.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is taking place, the bus is active. Only master devices can start a communication. They do this by causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

After the master issues a START condition, it sends a byte that indicates which slave device it wants to communicate with. This byte is called the address byte. Each device on an I²C bus has a unique 7-bit address to which it responds. Slaves can also have 10-bit addresses; see the I²C specification for details. The master sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to the slave device.

Every byte transmitted on the I²C bus, whether it is address or data, is acknowledged with an acknowledge bit. When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to clock the bit.

A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is present at that address to pull the line LOW.

When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated START condition.

The TLV320AIC3106-Q1 also responds to and acknowledges a General Call, which consists of the master issuing a command with a slave address byte of 00H.

Figure 29. I²C Write

Figure 30. I²C Read

In the case of an I²C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.

Similarly, in the case of an I²C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues an ACKNOWLEDGE, the slave takes over control of SDA bus and transmit for the next 8 clocks the data of the next incremental register.

9.5.4 I²C Bus Debug In A Glitched System

Occasionally, some systems may encounter noise or glitches on the I²C bus. In the unlikely event that this affects bus performance, then it can be useful to use the I²C Debug register. This feature terminates the I²C bus error allowing this I²C device and system to resume communications. The I²C bus error detector is enabled by default. The TLV320AIC3106-Q1 I²C error detector status can be read from Page 0, Register 107, Bit D0. If desired, the detector can be disabled by writing to Page 0, Register 107, Bit D2.

9.5.5 Digital Audio Data Serial Interface

Audio data is transferred from the host processor to the TLV320AIC3106-Q1 through the digital audio data serial interface, or audio bus. The audio bus on this device is very flexible, including left or right justified data options, support for I²S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master and slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly.

The data serial interface uses two sets of pins for communication between external devices, with the particular pin used controlled through register programming. This configuration is shown in Figure 31 below.

Figure 31. Alternate Audio Bus Mulitplexing Function

In cases where MFP3 is required for a secondary device digital input, the TLV320AIC3106-Q1 must be used in I²C mode (when in SPI mode, MFP3 is used as the SPI bus MOSI pin and thus cannot be used here as an alternate digital input source).

This mux capability allows the TLV320AIC3106-Q1 to communicate with two separate devices with independent I²S/PCM buses. Figure 32 shows an application example with an infotainment system that contains a Bluetooth transceiver and uses a PCM/I²S interface. The applications processor can be connected to the WCLK, BCLK, DIN, DOUT pins on the TLV320AIC3106-Q1, while a Bluetooth device with PCM interface can be connected to the GPIO1, GPIO2, MFP3, and DOUT pins on the TLV320AIC3106-Q1. By programming the registers through I²C control, the applications processor can determine which device is communicating with the TLV320AIC3106-Q1. This is attractive in cases where the TLV320AIC3106-Q1 can be configured to communicate data with the Bluetooth device, then the applications processor can be put into a low power sleep mode, while voice and audio transmission still occurs between the Bluetooth device and the TLV320AIC3106-Q1.

Figure 32. TLV320AIC3106-Q1 Connected To Multiple Audio Devices

The audio bus of the TLV320AIC3106-Q1 can be configured for left or right justified, I²S, DSP, or TDM modes of operation, where communication with standard audio PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock (WCLK or GPIO1) and bit clock (BCLK or GPIO2) can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors.

The word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.

The bit clock (BCLK or GPIO2) is used to clock in and out the digital audio data across the serial bus. When in Master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In continuous transfer mode, only the minimal number of bit clocks required to transfer the audio data are generated, so in general the number of bit clocks per frame is two times the data width. For example, if data width is chosen as 16-bits, then 32-bit clocks is generated per frame. If the bit clock signal in master mode is used by a PLL in another device, TI recommends the 16-bit or 32-bit data width selections be used. These cases result in a low jitter bit clock signal being generated, having frequencies of 32 × f_S or 64 × f_S. In the cases of 20‑bit and 24-bit data width in master mode, the bit clocks generated in each frame are not all be of equal period, due to the device not having a clean 40 × f_S or 48 × f_S clock signal readily available. The average frequency of the bit clock signal is still accurate in these cases (being 40 × f_S or 48 × f_S), but the resulting clock signal has higher jitter than in the 16-bit and 32-bit cases.

In 256-clock mode, a constant 256-bit clocks per frame are generated, independent of the data width chosen. The TLV320AIC3106-Q1 further includes programmability to 3 state the DOUT line during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus.

When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface are put into a 3-state output condition.

9.5.6 Right-Justified Mode

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

Figure 33. Right-Justified Serial Bus Mode Operation

9.5.7 Left-Justified Mode

In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock.

Figure 34. Left-Justified Serial Data Bus Mode Operation

9.5.8 I²S Mode

In I²S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

Figure 35. I²S Serial Data Bus Mode Operation

9.5.9 DSP Mode

In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.

Figure 36. DSP Serial Bus Mode Operation

9.5.10 TDM Data Transfer

Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit clock mode is selected, but TI recommends the use of either left-justified mode or DSP mode. By changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the serial data output driver (DOUT) can also be programmed to 3 state during all bit clocks except when valid data is being put onto the bus. This allows other codecs to be programmed with different offsets and to drive their data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores data on the bus except where it is expected based on the programmed offset.

The location of the data when an offset is programmed is different, depending on what transfer mode is selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in the frame. This differs from left-justified mode, where the left and right channel data are always a half-frame apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left and right channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in Figure 37 for the two cases.

Figure 37. DSP Mode And Left Justified Modes, Showing The
Effect Of A Programmed Data Word Offset

9.5.11 Audio Clock Generation

The audio converters in the TLV320AIC3106-Q1 require an internal audio master clock at a frequency of 256 × f_S(ref), which can be obtained in a variety of manners from an external clock signal applied to the device.

A more detailed diagram of the audio clock section of the TLV320AIC3106-Q1 is shown in Figure 38.

Figure 38. Audio Clock Generation Processing

The part can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a programmable divider or a PLL, to get the proper internal audio master clock required by the part. The BCLK or GPIO2 inputs can also be used to generate the internal audio master clock.

This design also allows the PLL to be used for an entirely separate purpose in a system, if the audio codec is not powered up. The user can supply a separate clock to GPIO2, route this through the PLL, with the resulting output clock driven out GPIO1, for use by other devices in the system.

A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.

When the PLL is disabled:

When the PLL is enabled:

P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

Examples:

If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified performance:

2 MHz ≤ (PLLCLK_IN / P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P) ≤ 110 MHz
4 ≤ J ≤ 55

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:

10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1

Example:

MCLK = 12 MHz and f_S(ref) = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

MCLK = 12 MHz and f_S(ref) = 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Table 7 lists several example cases of typical MCLK rates and how to program the PLL to achieve
f_S(ref) = 44.1 kHz or 48 kHz.

The TLV320AIC3106-Q1 can also output a separate clock on the GPIO1 pin. If the PLL is being used for the audio data converter clock, the M and N settings can be used to provide a divided version of the PLL output. If the PLL is not being used for the audio data converter clock, the PLL can still be enabled to provide a completely independent clock output on GPIO1. The formula for the GPIO1 clock output when PLL is enabled and CLKMUX_OUT is 0 is:

When CLKMUX_OUT is 1, regardless of whether PLL is enabled or disabled, the input to the clock output divider can be selected as MCLK, BCLK, or GPIO2. Is this case, the formula for the GPIO1 clock is:

Table 8. Page 0, Register 0: Page Select Register

Table 9. Page 0, Register 1: Software Reset Register

Table 10. Page 0, Register 2: Codec Sample Rate Select Register

Table 11. Page 0, Register 3: PLL Programming Register A

Table 12. Page 0, Register 4: PLL Programming Register B

Table 13. Page 0, Register 5: PLL Programming Register C

Table 14. Page 0, Register 6: PLL Programming Register D

Table 15. Page 0, Register 7: Codec Datapath Setup Register

Table 16. Page 0, Register 8: Audio Serial Data Interface Control Register A

Table 17. Page 0, Register 9: Audio Serial Data Interface Control Register B

Table 18. Page 0, Register 10: Audio Serial Data Interface Control Register C

Table 19. Page 0, Register 11: Audio Codec Overflow Flag Register

Table 20. Page 0, Register 12: Audio Codec Digital Filter Control Register

Table 21. Page 0, Register 13: Headset and Button Press Detection Register A

Table 22. Page 0, Register 14: Headset and Button Press Detection Register B

Table 23. Page 0, Register 15: Left ADC PGA Gain Control Register

Table 24. Page 0, Register 16: Right ADC PGA Gain Control Register

Table 25. Page 0, Register 17: MIC3L/R To Left ADC Control Register

Table 26. Page 0, Register 18: MIC3L/R To Right ADC Control Register

Table 27. Page 0, Register 19: LINE1L To Left ADC Control Register

Table 28. Page 0, Register 20: LINE2L To Left⁽¹⁾ ADC Control Register

Table 29. Page 0, Register 21: LINE1R To Left ADC Control Register

Table 30. Page 0, Register 22: LINE1R To Right ADC Control Register

Table 31. Page 0, Register 23: LINE2R To Right ADC Control Register

Table 32. Page 0, Register 24: LINE1L To Right ADC Control Register

Table 33. Page 0, Register 25: MICBIAS Control Register

Table 34. Page 0, Register 26: Left AGC Control Register A

Table 35. Page 0, Register 27: Left AGC Control Register B

Table 36. Page 0, Register 28: Left AGC Control Register C

Table 37. Page 0, Register 29: Right AGC Control Register A

Table 38. Page 0, Register 30: Right AGC Control Register B

Table 39. Page 0, Register 31: Right AGC Control Register C

Table 40. Page 0, Register 32: Left AGC Gain Register

Table 41. Page 0, Register 33: Right AGC Gain Register

Table 42. Page 0, Register 34: Left AGC Noise Gate Debounce Register

Table 43. Page 0, Register 35: Right AGC Noise Gate Debounce Register

Table 44. Page 0, Register 36: ADC Flag Register

Table 45. Page 0, Register 37: DAC Power And Output Driver Control Register

Table 46. Page 0, Register 38: High-Power Output Driver Control Register

Table 47. Page 0, Register 39: Reserved Register

Table 48. Page 0, Register 40: High Power Output Stage Control Register

Table 49. Page 0, Register 41: DAC Output Switching Control Register

Table 50. Page 0, Register 42: Output Driver Pop Reduction Register

Table 51. Page 0, Register 43: Left DAC Digital Volume Control Register

Table 52. Page 0, Register 44: Right DAC Digital Volume Control Register

9.6.1 Output Stage Volume Controls

A basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the output stage network, connected to each of the analog signals that route to the output stage. In addition, to enable completely independent mixing operations to be performed for each output driver, each analog signal coming into the output stage may have up to seven separate volume controls. These volume controls all have approximately 0.5-dB step programmability over most of the gain range, with steps increasing slightly at the lowest attenuations. Table 53 lists the detailed gain versus programmed setting for this basic volume control.

Based on the setting above, if BOTH LINE1 and LINE2 inputs are routed to the output at the same time, then the two switches used for the connection short the two input signals together on the output pins. The shorting resistance between the two input pins is two times the bypass switch resistance (R_DS(ON)). In general this condition of shorting must be avoided, as higher drive currents are likely to occur on the circuitry that feeds these two input pins of this device.

When programming any coefficient value in Page 1, the MSB register must always be written first, immediately followed by the LSB register. Even if only the MSB or LSB of the coefficient changes, both registers must be written in this sequence.