ZHCSBC4D May   2013  – May 2017 TAS5760MD

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Digital I/O Pins
    6. 7.6  Master Clock
    7. 7.7  Serial Audio Port
    8. 7.8  Protection Circuitry
    9. 7.9  Speaker Amplifier in All Modes
    10. 7.10 Headphone Amplifier and Line Driver
    11. 7.11 I²C Control Port
    12. 7.12 Typical Idle, Mute, Shutdown, Operational Power Consumption
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Speaker Amplifier Audio Signal Path
        1. 8.3.2.1 Serial Audio Port (SAP)
          1. 8.3.2.1.1 I²S Timing
          2. 8.3.2.1.2 Left-Justified
          3. 8.3.2.1.3 Right-Justified
        2. 8.3.2.2 DC Blocking Filter
        3. 8.3.2.3 Digital Boost and Volume Control
        4. 8.3.2.4 Digital Clipper
        5. 8.3.2.5 Closed-Loop Class-D Amplifier
      3. 8.3.3 Speaker Amplifier Protection Suite
        1. 8.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
        2. 8.3.3.2 DC Detect Protection
      4. 8.3.4 Headphone and Line Driver Amplifier
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Control Mode
        1. 8.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 8.4.1.2 Serial Audio Port in Hardware Control Mode
        3. 8.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
        4. 8.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
        5. 8.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
        6. 8.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
        7. 8.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
        8. 8.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
          1. 8.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 8.4.2 Software Control Mode
        1. 8.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 8.4.2.2 Serial Audio Port Controls
          1. 8.4.2.2.1 Serial Audio Port (SAP) Clocking
        3. 8.4.2.3 Parallel Bridge Tied Load Mode via Software Control
        4. 8.4.2.4 Speaker Amplifier Gain Structure
          1. 8.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
          2. 8.4.2.4.2 Considerations for Setting the Speaker Amplifier Gain Structure
          3. 8.4.2.4.3 Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
        5. 8.4.2.5 I²C Software Control Port
          1. 8.4.2.5.1 Setting the I²C Device Address
          2. 8.4.2.5.2 General Operation of the I²C Control Port
          3. 8.4.2.5.3 Writing to the I²C Control Port
          4. 8.4.2.5.4 Reading from the I²C Control Port
    5. 8.5 Register Maps
      1. 8.5.1 Control Port Registers - Quick Reference
      2. 8.5.2 Control Port Registers - Detailed Description
        1. 8.5.2.1  Device Identification Register (0x00)
        2. 8.5.2.2  Power Control Register (0x01)
        3. 8.5.2.3  Digital Control Register (0x02)
        4. 8.5.2.4  Volume Control Configuration Register (0x03)
        5. 8.5.2.5  Left Channel Volume Control Register (0x04)
        6. 8.5.2.6  Right Channel Volume Control Register (0x05)
        7. 8.5.2.7  Analog Control Register (0x06)
        8. 8.5.2.8  Reserved Register (0x07)
        9. 8.5.2.9  Fault Configuration and Error Status Register (0x08)
        10. 8.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
        11. 8.5.2.11 Digital Clipper Control 2 Register (0x10)
        12. 8.5.2.12 Digital Clipper Control 1 Register (0x11)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Using Software Control
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Startup Procedures- Software Control Mode
          2. 9.2.1.2.2 Shutdown Procedures- Software Control Mode
          3. 9.2.1.2.3 Component Selection and Hardware Connections
            1. 9.2.1.2.3.1 I²C Pullup Resistors
            2. 9.2.1.2.3.2 Digital I/O Connectivity
          4. 9.2.1.2.4 Recommended Startup and Shutdown Procedures
          5. 9.2.1.2.5 Headphone and Line Driver Amplifier
            1. 9.2.1.2.5.1 Charge-Pump Flying Capacitor and DR_VSS Capacitor
            2. 9.2.1.2.5.2 Decoupling Capacitors
            3. 9.2.1.2.5.3 Gain-Setting Resistor Ranges
            4. 9.2.1.2.5.4 Using the Line Driver Amplifier in the TAS5760MD as a Second-Order Filter
            5. 9.2.1.2.5.5 External Undervoltage Detection
            6. 9.2.1.2.5.6 Input-Blocking Capacitors
          6. 9.2.1.2.6 Gain-Setting Resistors
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Stereo BTL Using Hardware Control
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Startup Procedures- Hardware Control Mode
          2. 9.2.2.2.2 Shutdown Procedures- Hardware Control Mode
          3. 9.2.2.2.3 Digital I/O Connectivity
        3. 9.2.2.3 Application Curve
      3. 9.2.3 Mono PBTL Using Software Control
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Startup Procedures- Software Control Mode
          2. 9.2.3.2.2 Shutdown Procedures- Software Control Mode
          3. 9.2.3.2.3 Component Selection and Hardware Connections
            1. 9.2.3.2.3.1 I²C Pull-Up Resistors
            2. 9.2.3.2.3.2 Digital I/O Connectivity
        3. 9.2.3.3 Application Curve
      4. 9.2.4 Mono PBTL Using Hardware Control
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Startup Procedures- Hardware Control Mode
          2. 9.2.4.2.2 Shutdown Procedures- Hardware Control Mode
          3. 9.2.4.2.3 Component Selection and Hardware Connections
          4. 9.2.4.2.4 Digital I/O Connectivity
        3. 9.2.4.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB Footprint and Via Arrangement
            1. 11.1.3.2.1.1 Solder Stencil
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Temperature Ambient Operating Temperature, TA –25 85 °C
Ambient Storage Temperature, TS –40 125 °C
Supply Voltage AVDD Supply –0.3 V
PVDD Supply –0.3 V
DRVDD and DVDD Supply –0.3 4 V
DVDD Referenced Digital Input Voltages Digital Inputs referenced to DVDD supply –0.5 DVDD + 0.5 V
DRVDD Referenced Digital Input Voltages Digital Inputs referenced to DRVDD supply –0.5 DRVDD + 0.5 V
Headphone Load RHP 12.8 Ω
Line Driver Load RLD 600 Ω
Speaker Amplifier Output Voltage VSPK_OUTxx, measured at the output pin –0.3 V
Storage temperature range, Tstg –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
TA Ambient Operating Temperature –25 85 °C
AVDD AVDD Supply 4.5 V
PVDD PVDD Supply 4.5 V
DRVDD, DVDD DRVDD and DVDD Supply 2.8 3.63 V
VIH(DR) Input Logic HIGH for DVDD and DRVDD Referenced Digital Inputs DVDD V
VIL(DR) Input Logic LOW for DVDD and DRVDD Referenced Digital Inputs 0 V
RHP Headphone Load 16 Ω
RLD Line Driver Load 1 Ω
RSPK (BTL) Minimum Speaker Load in BTL Mode 4 Ω
RSPK (PBTL) Minimum Speaker Load in PBTL Mode 2 Ω

7.4 Thermal Information

THERMAL METRIC(1) TAS5760MD UNIT
DCA [HTSSOP] DCA [HTSSOP]
48 PIN(2) 48 PIN(3)
θJA Junction-to-ambient thermal resistance 60.3 30.2 °C/W
θJC(top) Junction-to-case (top) thermal resistance 16 14.3 °C/W
θJB Junction-to-board thermal resistance 12 12.7 °C/W
ψJT Junction-to-top characterization parameter 0.4 0.6 °C/W
ψJB Junction-to-board characterization parameter 11.9 12.7 °C/W
θJC(bottom) Junction-to-case (bottom) thermal resistance 0.8 0.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) JEDEC Standard 2 Layer Board
(3) JEDEC Standard 4 Layer Board

7.5 Digital I/O Pins

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH1 Input Logic HIGH threshold for DVDD Referenced Digital Inputs All digital pins except for DR_MUTE 70 %DVDD
VIL1 Input Logic LOW threshold for DVDD Referenced Digital Inputs All digital pins except for DR_MUTE 30 %DVDD
IIH1 Input Logic HIGH Current Level All digital pins except for DR_MUTE 15 µA
IIL1 Input Logic LOW Current Level All digital pins except for DR_MUTE –15 µA
VOH Output Logic HIGH Voltage Level IOH = 2 mA 90 %DVDD
VOL Output Logic LOW Voltage Level IOH = -2 mA 10 %DVDD
VIH2 Input Logic HIGH threshold for DRVDD Referenced Digital Inputs For DR_MUTE Pin 60 %DRVDD
VIL2 Input Logic LOW threshold for DRVDD Referenced Digital Inputs For DR_MUTE Pin 40 %DRVDD
IIH2 Input Logic HIGH Current Level For DR_MUTE Pin 1 µA
IIL2 Input Logic LOW Current Level For DR_MUTE Pin –1 µA

7.6 Master Clock

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DMCLK Allowable MCLK Duty Cycle 45% 50% 55%
fMCLK Supported MCLK Frequencies Values include: 128, 192, 256, 384, 512. 128 512 fS

7.7 Serial Audio Port

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DSCLK Allowable SCLK Duty Cycle 45% 50% 55%
Required LRCK to SCLK Rising Edge 15 ns
tHLD Required SDIN Hold Time after SCLK Rising Edge 15 ns
tsu Required SDIN Setup Time before SCLK Rising Edge 15 ns
fS Supported Input Sample Rates Sample rates above 48kHz supported by "double speed mode," which is activated through the I²C control port 32 96 kHz
fSCLK Supported SCLK Frequencies Values include: 32, 48, 64 32 64 fS

7.8 Protection Circuitry

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OVERTHRES(PVDD) PVDD Overvoltage Error Threshold PVDD Rising V
OVEFTHRES(PVDD) PVDD Overvoltage Error Threshold PVDD Falling V
UVEFTHRES(PVDD) PVDD Undervoltage Error (UVE) Threshold PVDD Falling 3.95 V
UVERTHRES(PVDD) PVDD UVE Threshold (PVDD Rising) PVDD Rising 4.15 V
OTETHRES Overtemperature Error (OTE) Threshold 150 °C
OTEHYST Overtemperature Error (OTE) Hysteresis 15 °C
OCETHRES Overcurrent Error (OCE) Threshold for each BTL Output PVDD= 15V, TA = 25 °C 7 A
DCETHRES DC Error (DCE) Threshold PVDD= 12V, TA = 25 °C 2.6 V
TSPK_FAULT Speaker Amplifier Fault Time Out period DC Detect Error 650 ms
OTE or OCP Fault 1.3 s
UVETHRES(DRVDD) Undervoltage Error (UVE) Threshold for headphone and line driver amplifier Sensed on DR_UVE pin 1.25 V
ILIMIT(DR) Current Sourcing Limit of the Headphone and line driver amplifier 68 mA

7.9 Speaker Amplifier in All Modes

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AV00 Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 00 Hardware Control Mode (Additional gain settings available in Software Control Mode)(1) 25.2 dBV
AV01 Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 01 Hardware Control Mode (Additional gain settings available in Software Control Mode)(1) 28.6 dBV
AV10 Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 10 Hardware Control Mode (Additional gain settings available in Software Control Mode)(1) 31 dBV
AV11 Speaker Amplifier Gain with SPK_GAIN[1:0] Pins = 11 (This setting places the device in Software Control Mode) (Set via I²C)
|VOS|(SPK_AMP) Speaker Amplifier DC Offset BTL, Worst case over voltage, gain settings 10 mV
PBTL, Worst case over voltage, gain settings 15 mV
fSPK_AMP(0) Speaker Amplifier Switching Frequency when PWM_FREQ Pin = 0 (Hardware Control Mode. Additional switching rates available in Software Control Mode.) 16 fS
fSPK_AMP(1) Speaker Amplifier Switching Frequency when PWM_FREQ Pin = 1 (Hardware Control Mode. Additional switching rates available in Software Control Mode.) 8 fS
RDS(ON) On Resistance of Output MOSFET (both high-side and low-side) PVDD = 15 V, TA = 25 °C, Die Only 120 mΩ
PVDD= 15V, TA = 25 °C, Includes: Die, Bond Wires, Leadframe 150 mΩ
fC –3-dB Corner Frequency of High-Pass Filter fS = 44.1 kHz 3.7 Hz
fS = 48 kHz 4
fS = 88.2 kHz 7.4
fS = 96 kHz 8
(1) The digital boost block contributes +6dB of gain to this value. The audio signal must be kept below -6dB to avoid clipping the digital audio path.

7.10 Headphone Amplifier and Line Driver

input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input to Output Attenuation when muted 80 dB
|VOS|(DR) Output Offset Voltage of Headphone Amplifier and Line Driver 0.5 mV
fCP Charge Pump Switching Frequency 200 300 400 kHz
ICN(HP) Idle Channel Noise R(HP) = 32 Ω, A-Weighted 13 µVrms
ICN(LD) Idle Channel Noise R(LD) = 3 kΩ, A-Weighted 11 µVrms
Po(HP) Headphone Amplifier Output Power R(HP) = 16 Ω, THD+N = 1%, Outputs in Phase 40 mW
PSRR(DR) Power Supply Rejection Ratio of Headphone Amplifier and Line Driver 80 dB
SNR(HP) Signal to Noise Ratio (Referenced to 25 mW Output Signal), R(HP) = 16 Ω, A-Weighted 96 dB
SNR(LD) Signal to Noise Ratio (Referenced to 2 Vrms Output Signal), R(LD) = 3 kΩ, A-Weighted 90 105 dB
THD+N(HP) Total Harmonic Distortion and Noise for the Headphone Amplifier PO(HP) = 10 mW 0.01%
THD+N(LD) Total Harmonic Distortion and Noise for the Line Driver VO(LD) = 2 Vrms 0.002%
Vo(LD) Line Driver Output Voltage THD+N = 1%, R(LD) = 3kΩ, Outputs in Phase 2 2.4 Vrms
X-Talk(HP) Cross-talk (worst case between LtoR and RtoL coupling) PO(HP) = 20 mW –90 dB
X-Talk(LD) Cross-talk (worst case between LtoR and RtoL coupling) Vo = 1 Vrms –111 dB
ZO(DR) Output Impedance when muted DR_MUTE = LOW 110 mΩ
IMUTE(DR) Current drawn from DRVDD supply in mute DR_MUTE = LOW 12 mA
IDRVDD(HP) Current drawn from DRVDD supply with headphone DR_MUTE = HIGH, PO(HP) = 25 mW, Input = 1kHz 60 mA
IDRVDD(LD) Current drawn from DRVDD supply with line driver DR_MUTE = HIGH, VO(LD) = 2 Vrms, Input = 1kHz 12 mA

7.11 I²C Control Port

specifications are over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CL(I²C) Allowable Load Capacitance for Each I²C Line 400 pF
fSCL Support SCL frequency No Wait States 400 kHz
tbuf Bus Free time between STOP and START conditions 1.3 µS
tf(I²C) Rise Time, SCL and SDA 300 ns
th1(I²C) Hold Time, SCL to SDA 0 ns
th2(I²C) Hold Time, START condition to SCL 0.6 µs
tI²C(start) I²C Startup Time 12 mS
tr(I²C) Rise Time, SCL and SDA 300 ns
tsu1(I²C) Setup Time, SDA to SCL 100 ns
tsu2(I²C) Setup Time, SCL to START condition 0.6 µS
tsu3(I²C) Setup Time, SCL to STOP condition 0.6 µS
Tw(H) Required Pulse Duration, SCL HIGH 0.6 µS
Tw(L) Required Pulse Duration, SCL LOW 1.3 µS

7.12 Typical Idle, Mute, Shutdown, Operational Power Consumption

input signal is 1 kHz Sine, specifications are over operating free-air temperature range (unless otherwise noted)
VPVDD
[V]		 RSPK
[Ω]		 SPEAKER AMPLIFIER STATE IPVDD+AVDD
[mA]		 IDVDD
[mA]		 PDISS
[W]
6 4 fSPK_AMP = 384kHz Idle 23.48 3.73 0.15
8 23.44 3.72 0.15
4 Mute 23.53 3.72 0.15
8 23.46 3.72 0.15
4 Sleep 13.26 0.48 0.08
8 13.27 0.53 0.08
4 Shutdown 0.046 0.04 0
8 0.046 0.03 0
4 fSPK_AMP = 768kHz Idle 30.94 3.71 0.2
8 30.94 3.71 0.2
4 Mute 29.37 3.71 0.19
8 29.39 3.71 0.19
4 Sleep 13.24 0.5 0.08
8 13.23 0.52 0.08
4 Shutdown 0.046 0.03 0
8 0.046 0.03 0
4 fSPK_AMP = 1152kHz Idle 39.39 3.7 0.25
8 39.43 3.7 0.25
4 Mute 36.91 3.7 0.23
8 36.9 3.69 0.23
4 Sleep 13.17 0.53 0.08
8 13.13 0.45 0.08
4 Shutdown 0.046 0.03 0
8 0.046 0.03 0
12 4 fSPK_AMP = 384kHz Idle 32.95 3.74 0.41
8 32.93 3.73 0.41
4 Mute 32.98 3.73 0.41
8 32.97 3.73 0.41
4 Sleep 12.71 0.47 0.15
8 12.75 0.5 0.15
4 Shutdown 0.053 0.04 0
8 0.053 0.04 0
4 fSPK_AMP = 768kHz Idle 44.84 3.73 0.55
8 44.82 3.73 0.55
4 Mute 42.71 3.72 0.52
8 42.66 3.72 0.52
4 Sleep 12.71 0.49 0.15
8 12.73 0.52 0.15
4 Shutdown 0.063 0.03 0
8 0.053 0.03 0
4 fSPK_AMP = 1152kHz Idle 59.3 3.73 0.72
8 59.3 3.73 0.72
4 Mute 55.74 3.72 0.68
8 55.74 3.72 0.68
4 Sleep 12.67 0.49 0.15
8 12.61 0.43 0.15
4 Shutdown 0.053 0.02 0
8 0.053 0.03 0