ZHCSFX6C March   2016  – May 2017 TAS5753MD

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Speaker Amplifier Characteristics in All Modes
    7. 6.7  Speaker Amplifier Characteristics in Stereo Bridge Tied Load (BTL) Mode
    8. 6.8  Speaker Amplifier Characteristics in Stereo Post-Filter Parallel Bridge Tied Load (Post-Filter PBTL) Mode
    9. 6.9  Headphone Amplifier and Line Driver Characteristics
    10. 6.10 Protection Circuitry Characteristics
    11. 6.11 I²C Interface Timing Requirements
    12. 6.12 Serial Audio Port Timing Requirements
    13. 6.13 Typical Electrical Power Consumption
    14. 6.14 Typical Characteristics
      1. 6.14.1 Typical Characteristics - BTL Mode
      2. 6.14.2 Typical Characteristics - PBTL Mode
      3. 6.14.3 Typical Characteristics - Headphone Amplifier
      4. 6.14.4 Typical Characteristics - Line Driver
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Audio Signal Processing Overview
    4. 7.4 Feature Description
      1. 7.4.1 Clock, Autodetection, and PLL
      2. 7.4.2 PWM Section
      3. 7.4.3 PWM Level Meter
      4. 7.4.4 Automatic Gain Limiter (AGL)
      5. 7.4.5 Headphone/Line Amplifier
      6. 7.4.6 Fault Indication
      7. 7.4.7 SSTIMER Pin Functionality
      8. 7.4.8 Device Protection System
        1. 7.4.8.1 Overcurrent (OC) Protection With Current Limiting
        2. 7.4.8.2 Overtemperature Protection
        3. 7.4.8.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
    5. 7.5 Device Functional Modes
      1. 7.5.1 Serial Audio Port Operating Modes
      2. 7.5.2 Communication Port Operating Modes
      3. 7.5.3 Speaker Amplifier Modes
        1. 7.5.3.1 Stereo Mode
        2. 7.5.3.2 Mono Mode
    6. 7.6 Programming
      1. 7.6.1 I²C Serial Control Interface
        1. 7.6.1.1 General I²C Operation
        2. 7.6.1.2 I²C Slave Address
          1. 7.6.1.2.1 I²C Device Address Change Procedure
        3. 7.6.1.3 Single- and Multiple-Byte Transfers
        4. 7.6.1.4 Single-Byte Write
        5. 7.6.1.5 Multiple-Byte Write
        6. 7.6.1.6 Single-Byte Read
        7. 7.6.1.7 Multiple-Byte Read
      2. 7.6.2 Serial Interface Control and Timing
        1. 7.6.2.1 Serial Data Interface
        2. 7.6.2.2 I²S Timing
        3. 7.6.2.3 Left-Justified
        4. 7.6.2.4 Right-Justified
      3. 7.6.3 26-Bit 3.23 Number Format
    7. 7.7 Register Maps
      1. 7.7.1 Register Summary
      2. 7.7.2 Detailed Register Descriptions
        1. 7.7.2.1  Clock Control Register (0x00)
        2. 7.7.2.2  Device ID Register (0x01)
        3. 7.7.2.3  Error Status Register (0x02)
        4. 7.7.2.4  System Control Register 1 (0x03)
        5. 7.7.2.5  Serial Data Interface Register (0x04)
        6. 7.7.2.6  System Control Register 2 (0x05)
        7. 7.7.2.7  Soft Mute Register (0x06)
        8. 7.7.2.8  Volume Registers (0x07, 0x08, 0x09)
        9. 7.7.2.9  Volume Configuration Register (0x0E)
        10. 7.7.2.10 Modulation Limit Register (0x10)
        11. 7.7.2.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
        12. 7.7.2.12 PWM Shutdown Group Register (0x19)
        13. 7.7.2.13 Start/Stop Period Register (0x1A)
        14. 7.7.2.14 Oscillator Trim Register (0x1B)
        15. 7.7.2.15 BKND_ERR Register (0x1C)
        16. 7.7.2.16 Input Multiplexer Register (0x20)
        17. 7.7.2.17 PWM Output MUX Register (0x25)
        18. 7.7.2.18 AGL Control Register (0x46)
        19. 7.7.2.19 PWM Switching Rate Control Register (0x4F)
        20. 7.7.2.20 Bank Switch and EQ Control (0x50)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection Criteria
        1. 8.1.1.1 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
        2. 8.1.1.2 Amplifier Output Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Bridge Tied Load Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Component Selection and Hardware Connections
          2. 8.2.1.2.2 Control and Software Integration
          3. 8.2.1.2.3 I²C Pullup Resistors
          4. 8.2.1.2.4 Digital I/O Connectivity
          5. 8.2.1.2.5 Recommended Startup and Shutdown Procedures
            1. 8.2.1.2.5.1 Start-Up Sequence
            2. 8.2.1.2.5.2 Normal Operation
            3. 8.2.1.2.5.3 Shutdown Sequence
            4. 8.2.1.2.5.4 Power-Down Sequence
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Mono Parallel Bridge Tied Load Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
      3. 8.2.3 Stereo BTL Configuration with Headphone and Line Driver Amplifier Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Performance Plots
      4. 8.2.4 Mono Parallel Bridge-Tied Load Configuration with Headphone and Line Driver Amplifier
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Decoupling Capacitors
      2. 10.1.2 Thermal Performance and Grounding
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1 特性

  • 音频输入/输出
    • 支持具有 4Ω 负载的 BTL 配置
    • 一个立体声串行音频输入
    • I2C 地址选择引脚
    • 支持 44.1kHz 和 48kHz 的采样率 (LJ/RJ/I2S)
  • 耳机放大器和线路驱动器
    • 独立通道音量控制，增益为静音到 24dB 增益（步长为 0.125dB）
    • 可编程 3 波段自动增益限制 (AGL)
    • 20 个可编程的 Biquad，适用于扬声器均衡 (EQ) 及其他音频处理 特性
  • 通用 特性
    • I2C 串行控制接口可在无 MCLK 的情况下运行
    • 自动速率检测
    • 过热保护、短路保护和欠压保护
    • 105dB SNR，A 加权，以满量程 (0dB) 为基准
    • 效率高达 90%
    • AD、BD 和三重调制
    • 脉宽调制 (PWM) 电平计量
    • 通过 4.5V 至 24V 的 PVDD 工作

2 应用

  • LCD TV、LED TV
  • 低成本条形音箱
  • 通用低成本音频设备

3 说明

TAS5753MD 器件是一款高效数字输入音频放大器，用于驱动采用桥接负载 (BTL) 配置的立体声扬声器。一个串行数据输入可处理最多两个离散音频通道并能与大多数数字音频处理器和 MPEG 解码器无缝整合。此器件可接受宽范围的输入数据和数据传输速率。一个完全可编程数据路径将这些通道路由至内部扬声器驱动器。

TAS5753MD 器件仅用作从器件，以接收外部提供的所有时钟。TAS5753MD 器件采用开关频率介于 288kHz 和 384kHz 之间的 PWM 载波，具体取决于输入采样率。与四阶噪声整形器结合的过采样可提供一个白噪音基准以及 20Hz 至 20kHz 的出色动态范围。器件具有一个集成式 DirectPath™耳机放大器和线路驱动器，用于提高系统级集成度并降低总体解决方案成本。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TAS5753MD HTSSOP (48) 12.50mm x 6.10mm
  1. 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

输出功率与电源电压

TAS5753MD D001_SLASEA5.gif

功能方框图

TAS5753MD fbd_slasea5_tas8733.gif