ZHCSHK8B October   2017  – October 2018 TAS2770

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      功能方框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 PDM Port Timing Requirements
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Mode and Address Selection
      2. 8.3.2 General I2C Operation
      3. 8.3.3 Single-Byte and Multiple-Byte Transfers
      4. 8.3.4 Single-Byte Write
      5. 8.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6 Single-Byte Read
      7. 8.3.7 Multiple-Byte Read
      8. 8.3.8 Register Organization
    4. 8.4 Device Functional Modes
      1. 8.4.1  PDM Input
      2. 8.4.2  TDM Port
      3. 8.4.3  Playback Signal Path
        1. 8.4.3.1 High Pass Filter
        2. 8.4.3.2 Digital Volume Control and Amplifier Output Level
        3. 8.4.3.3 Audio Playback Selection
        4. 8.4.3.4 Battery Tracking Limiter with Brown Out Prevention
        5. 8.4.3.5 Inter Chip Limiter Alignment
          1. 8.4.3.5.1 TDM Mode
        6. 8.4.3.6 Class-D Settings
      4. 8.4.4  SAR ADC
      5. 8.4.5  IV Sense
      6. 8.4.6  Clocks and PLL
      7. 8.4.7  Operational Modes
        1. 8.4.7.1 Hardware Shutdown
        2. 8.4.7.2 Software Shutdown
        3. 8.4.7.3 Mute
        4. 8.4.7.4 Active
        5. 8.4.7.5 Mode Control and Software Reset
      8. 8.4.8  Faults and Status
      9. 8.4.9  Power Sequencing Requirements
      10. 8.4.10 Digital Input Pull Downs
    5. 8.5 Register Maps
      1. 8.5.1 Register Summary Table Book=0x00 Page=0x00
      2. 8.5.2 Register Maps
        1. 8.5.2.1  PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
          1. Table 82. Device Page Field Descriptions
        2. 8.5.2.2  SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
          1. Table 83. Software Reset Field Descriptions
        3. 8.5.2.3  PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
          1. Table 84. Power Control Field Descriptions
        4. 8.5.2.4  PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
          1. Table 85. Playback Configuration 0 Field Descriptions
        5. 8.5.2.5  PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
          1. Table 86. Playback Configuration 1 Field Descriptions
        6. 8.5.2.6  PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
          1. Table 87. Playback Configuration 2 Field Descriptions
        7. 8.5.2.7  PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
          1. Table 88. Playback Configuration 3 Field Descriptions
        8. 8.5.2.8  MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
          1. Table 89. Misc Configuration Field Descriptions
        9. 8.5.2.9  PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
          1. Table 90. PDM Input Register 0 Field Descriptions
        10. 8.5.2.10 PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
          1. Table 91. PDM Configuration 1 Field Descriptions
        11. 8.5.2.11 TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
          1. Table 92. TDM Configuration 0 Field Descriptions
        12. 8.5.2.12 TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
          1. Table 93. TDM Configuration 1 Field Descriptions
        13. 8.5.2.13 TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
          1. Table 94. TDM Configuration 2 Field Descriptions
        14. 8.5.2.14 TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
          1. Table 95. TDM Configuration 3 Field Descriptions
        15. 8.5.2.15 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
          1. Table 96. TDM Configuration 4 Field Descriptions
        16. 8.5.2.16 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
          1. Table 97. TDM Configuration 5 Field Descriptions
        17. 8.5.2.17 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
          1. Table 98. TDM Configuration 6 Field Descriptions
        18. 8.5.2.18 TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
          1. Table 99. TDM Configuration 7 Field Descriptions
        19. 8.5.2.19 TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
          1. Table 100. TDM Configuration 8 Field Descriptions
        20. 8.5.2.20 TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
          1. Table 101. TDM Configuration 9 Field Descriptions
        21. 8.5.2.21 TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
          1. Table 102. TDM Configuration 10 Field Descriptions
        22. 8.5.2.22 LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
          1. Table 103. Limiter Configuration 0 Field Descriptions
        23. 8.5.2.23 LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
          1. Table 104. Limiter Configuration 1 Field Descriptions
        24. 8.5.2.24 LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
          1. Table 105. Limiter Configuration 2 Field Descriptions
        25. 8.5.2.25 LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
          1. Table 106. Limiter Configuration 3 Field Descriptions
        26. 8.5.2.26 LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
          1. Table 107. Limiter Configuration 4 Field Descriptions
        27. 8.5.2.27 LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
          1. Table 108. Limiter Configuration 5 Field Descriptions
        28. 8.5.2.28 BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
          1. Table 109. Brown Out Prevention 0 Field Descriptions
        29. 8.5.2.29 BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
          1. Table 110. Brown Out Prevention 1 Field Descriptions
        30. 8.5.2.30 BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
          1. Table 111. Brown Out Prevention 2 Field Descriptions
        31. 8.5.2.31 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
          1. Table 112. Inter Chip Limiter Alignment 0 Field Descriptions
        32. 8.5.2.32 ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
          1. Table 113. Inter Chip Limiter Alignment 1 Field Descriptions
        33. 8.5.2.33 INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
          1. Table 114. Interrupt Mask 0 Field Descriptions
        34. 8.5.2.34 INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
          1. Table 115. Interrupt Mask 1 Field Descriptions
        35. 8.5.2.35 INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
          1. Table 116. Live Interrupt Readback 0 Field Descriptions
        36. 8.5.2.36 INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
          1. Table 117. Live Interrupt Readback 1 Field Descriptions
        37. 8.5.2.37 INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
          1. Table 118. Latched Interrupt Readback 0 Field Descriptions
        38. 8.5.2.38 INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
          1. Table 119. Latched Interrupt Readback 1 Field Descriptions
        39. 8.5.2.39 INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
          1. Table 1.   INT_LTCH2 Register Address: 0x26
          2. Table 120. INT_LTCH2 Field Descriptions
        40. 8.5.2.40 VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
          1. Table 121. SAR ADC Conversion 0 Field Descriptions
        41. 8.5.2.41 VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
          1. Table 122. SAR ADC Conversion 1 Field Descriptions
        42. 8.5.2.42 TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
          1. Table 123. SAR ADC Conversion 2 Field Descriptions
        43. 8.5.2.43 TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
          1. Table 124. SAR ADC Conversion 2 Field Descriptions
        44. 8.5.2.44 INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
          1. Table 125. Interrupt Configuration Field Descriptions
        45. 8.5.2.45 DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
          1. Table 126. Digital Input Pin Pull Down Field Descriptions
        46. 8.5.2.46 MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
          1. Table 127. Misc Configuration Field Descriptions
        47. 8.5.2.47 CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
          1. Table 128. Clock Configuration Field Descriptions
        48. 8.5.2.48 TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
          1. Table 129. TDM Clock detection monitor Field Descriptions
        49. 8.5.2.49 REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
          1. Table 130. Revision and PG ID Field Descriptions
        50. 8.5.2.50 I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
          1. Table 131. I2C Checksum Field Descriptions
        51. 8.5.2.51 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
          1. Table 132. Device Book Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Overview
        2. 9.2.2.2 Select Input Capacitance
        3. 9.2.2.3 Select Decoupling Capacitors
        4. 9.2.2.4 Select Bootstrap Capacitors
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Initial Device Configuration - Auto Rate
      2. 9.3.2 Initial Device Configuration - 48 kHz
      3. 9.3.3 Initial Device Configuration - 44.1 kHz
      4. 9.3.4 Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5 Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6 Device Mute
      7. 9.3.7 Device Un-Mute
      8. 9.3.8 Device Sleep
      9. 9.3.9 Device Wake
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YFF|30
  • RJQ|26
订购信息

Register Summary Table Book=0x00 Page=0x00

Addr Register Description Section
0x00 PAGE Device Page PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
0x01 SW_RESET Software Reset SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
0x02 PWR_CTL Power Control PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
0x03 PB_CFG0 Playback Configuration 0 PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
0x04 PB_CFG1 Playback Configuration 1 PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
0x05 PB_CFG2 Playback Configuration 2 PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
0x06 PB_CFG3 Playback Configuration 3 PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
0x07 MISC_CFG Misc Configuration MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
0x08 PDM_CFG0 PDM Input Register 0 PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
0x09 PDM_CFG1 PDM Configuration 1 PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
0x0A TDM_CFG0 TDM Configuration 0 TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
0x0B TDM_CFG1 TDM Configuration 1 TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
0x0C TDM_CFG2 TDM Configuration 2 TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
0x0D TDM_CFG3 TDM Configuration 3 TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
0x0E TDM_CFG4 TDM Configuration 4 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
0x0F TDM_CFG5 TDM Configuration 5 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
0x10 TDM_CFG6 TDM Configuration 6 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
0x11 TDM_CFG7 TDM Configuration 7 TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
0x12 TDM_CFG8 TDM Configuration 8 TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
0x13 TDM_CFG9 TDM Configuration 9 TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
0x14 TDM_CFG10 TDM Configuration 10 TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
0x15 LIM_CFG0 Limiter Configuration 0 LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
0x16 LIM_CFG1 Limiter Configuration 1 LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
0x17 LIM_CFG2 Limiter Configuration 2 LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
0x18 LIM_CFG3 Limiter Configuration 3 LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
0x19 LIM_CFG4 Limiter Configuration 4 LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
0x1A LIM_CFG5 Limiter Configuration 5 LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
0x1B BOP_CFG0 Brown Out Prevention 0 BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
0x1C BOP_CFG1 Brown Out Prevention 1 BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
0x1D BOP_CFG2 Brown Out Prevention 2 BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
0x1E ICLA_CFG0 Inter Chip Limiter Alignment 0 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
0x1F ICLA_CFG1 Inter Chip Limiter Alignment 1 ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
0x20 INT_MASK0 Interrupt Mask 0 INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
0x21 INT_MASK1 Interrupt Mask 1 INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
0x22 INT_LIVE0 Live Interrupt Readback 0 INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
0x23 INT_LIVE1 Live Interrupt Readback 1 INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
0x24 INT_LTCH0 Latched Interrupt Readback 0 INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
0x25 INT_LTCH1 Latched Interrupt Readback 1 INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
0x27 VBAT_MSB SAR ADC Conversion 0 VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
0x28 VBAT_LSB SAR ADC Conversion 1 VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
0x29 TEMP_MSB SAR ADC Conversion 2 TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
0x2A TEMP_LSB SAR ADC Conversion 2 TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
0x30 INT_CFG Interrupt Configuration INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
0x31 DIN_PD Digital Input Pin Pull Down DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
0x32 MISC_IRQ Misc Configuration MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
0x3C CLOCK_CFG Clock Configuration CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
0x77 TDM_DET TDM Clock detection monitor TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
0x7D REV_ID Revision and PG ID REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
0x7E I2C_CKSUM I2C Checksum I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
0x7F BOOK Device Book BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]