ZHCSHK8B October 2017 – October 2018 TAS2770
The device enters Hardware Shutdown mode if the SDZ pin is asserted low. In Hardware Shutdown mode, the device consumes the minimum quiescent current from AVDD and VBAT supplies. All registers loose state in this mode and communication is disabled (via I2C).
If SDZ is asserted low while audio is playing, the device will ramp down volume on the audio, stop the Class-D switching, power down analog and digital blocks and finally put the device into Hardware Shutdown mode.
When SDZ is released, the device will sample the MODE pin and enter the selected operational mode (i.e. either TDM/I2C).