ZHCSHK8B October   2017  – October 2018 TAS2770

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      功能方框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 PDM Port Timing Requirements
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Mode and Address Selection
      2. 8.3.2 General I2C Operation
      3. 8.3.3 Single-Byte and Multiple-Byte Transfers
      4. 8.3.4 Single-Byte Write
      5. 8.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6 Single-Byte Read
      7. 8.3.7 Multiple-Byte Read
      8. 8.3.8 Register Organization
    4. 8.4 Device Functional Modes
      1. 8.4.1  PDM Input
      2. 8.4.2  TDM Port
      3. 8.4.3  Playback Signal Path
        1. 8.4.3.1 High Pass Filter
        2. 8.4.3.2 Digital Volume Control and Amplifier Output Level
        3. 8.4.3.3 Audio Playback Selection
        4. 8.4.3.4 Battery Tracking Limiter with Brown Out Prevention
        5. 8.4.3.5 Inter Chip Limiter Alignment
          1. 8.4.3.5.1 TDM Mode
        6. 8.4.3.6 Class-D Settings
      4. 8.4.4  SAR ADC
      5. 8.4.5  IV Sense
      6. 8.4.6  Clocks and PLL
      7. 8.4.7  Operational Modes
        1. 8.4.7.1 Hardware Shutdown
        2. 8.4.7.2 Software Shutdown
        3. 8.4.7.3 Mute
        4. 8.4.7.4 Active
        5. 8.4.7.5 Mode Control and Software Reset
      8. 8.4.8  Faults and Status
      9. 8.4.9  Power Sequencing Requirements
      10. 8.4.10 Digital Input Pull Downs
    5. 8.5 Register Maps
      1. 8.5.1 Register Summary Table Book=0x00 Page=0x00
      2. 8.5.2 Register Maps
        1. 8.5.2.1  PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
          1. Table 82. Device Page Field Descriptions
        2. 8.5.2.2  SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
          1. Table 83. Software Reset Field Descriptions
        3. 8.5.2.3  PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
          1. Table 84. Power Control Field Descriptions
        4. 8.5.2.4  PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
          1. Table 85. Playback Configuration 0 Field Descriptions
        5. 8.5.2.5  PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
          1. Table 86. Playback Configuration 1 Field Descriptions
        6. 8.5.2.6  PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
          1. Table 87. Playback Configuration 2 Field Descriptions
        7. 8.5.2.7  PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
          1. Table 88. Playback Configuration 3 Field Descriptions
        8. 8.5.2.8  MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
          1. Table 89. Misc Configuration Field Descriptions
        9. 8.5.2.9  PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
          1. Table 90. PDM Input Register 0 Field Descriptions
        10. 8.5.2.10 PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
          1. Table 91. PDM Configuration 1 Field Descriptions
        11. 8.5.2.11 TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
          1. Table 92. TDM Configuration 0 Field Descriptions
        12. 8.5.2.12 TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
          1. Table 93. TDM Configuration 1 Field Descriptions
        13. 8.5.2.13 TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
          1. Table 94. TDM Configuration 2 Field Descriptions
        14. 8.5.2.14 TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
          1. Table 95. TDM Configuration 3 Field Descriptions
        15. 8.5.2.15 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
          1. Table 96. TDM Configuration 4 Field Descriptions
        16. 8.5.2.16 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
          1. Table 97. TDM Configuration 5 Field Descriptions
        17. 8.5.2.17 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
          1. Table 98. TDM Configuration 6 Field Descriptions
        18. 8.5.2.18 TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
          1. Table 99. TDM Configuration 7 Field Descriptions
        19. 8.5.2.19 TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
          1. Table 100. TDM Configuration 8 Field Descriptions
        20. 8.5.2.20 TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
          1. Table 101. TDM Configuration 9 Field Descriptions
        21. 8.5.2.21 TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
          1. Table 102. TDM Configuration 10 Field Descriptions
        22. 8.5.2.22 LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
          1. Table 103. Limiter Configuration 0 Field Descriptions
        23. 8.5.2.23 LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
          1. Table 104. Limiter Configuration 1 Field Descriptions
        24. 8.5.2.24 LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
          1. Table 105. Limiter Configuration 2 Field Descriptions
        25. 8.5.2.25 LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
          1. Table 106. Limiter Configuration 3 Field Descriptions
        26. 8.5.2.26 LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
          1. Table 107. Limiter Configuration 4 Field Descriptions
        27. 8.5.2.27 LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
          1. Table 108. Limiter Configuration 5 Field Descriptions
        28. 8.5.2.28 BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
          1. Table 109. Brown Out Prevention 0 Field Descriptions
        29. 8.5.2.29 BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
          1. Table 110. Brown Out Prevention 1 Field Descriptions
        30. 8.5.2.30 BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
          1. Table 111. Brown Out Prevention 2 Field Descriptions
        31. 8.5.2.31 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
          1. Table 112. Inter Chip Limiter Alignment 0 Field Descriptions
        32. 8.5.2.32 ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
          1. Table 113. Inter Chip Limiter Alignment 1 Field Descriptions
        33. 8.5.2.33 INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
          1. Table 114. Interrupt Mask 0 Field Descriptions
        34. 8.5.2.34 INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
          1. Table 115. Interrupt Mask 1 Field Descriptions
        35. 8.5.2.35 INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
          1. Table 116. Live Interrupt Readback 0 Field Descriptions
        36. 8.5.2.36 INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
          1. Table 117. Live Interrupt Readback 1 Field Descriptions
        37. 8.5.2.37 INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
          1. Table 118. Latched Interrupt Readback 0 Field Descriptions
        38. 8.5.2.38 INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
          1. Table 119. Latched Interrupt Readback 1 Field Descriptions
        39. 8.5.2.39 INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
          1. Table 1.   INT_LTCH2 Register Address: 0x26
          2. Table 120. INT_LTCH2 Field Descriptions
        40. 8.5.2.40 VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
          1. Table 121. SAR ADC Conversion 0 Field Descriptions
        41. 8.5.2.41 VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
          1. Table 122. SAR ADC Conversion 1 Field Descriptions
        42. 8.5.2.42 TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
          1. Table 123. SAR ADC Conversion 2 Field Descriptions
        43. 8.5.2.43 TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
          1. Table 124. SAR ADC Conversion 2 Field Descriptions
        44. 8.5.2.44 INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
          1. Table 125. Interrupt Configuration Field Descriptions
        45. 8.5.2.45 DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
          1. Table 126. Digital Input Pin Pull Down Field Descriptions
        46. 8.5.2.46 MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
          1. Table 127. Misc Configuration Field Descriptions
        47. 8.5.2.47 CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
          1. Table 128. Clock Configuration Field Descriptions
        48. 8.5.2.48 TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
          1. Table 129. TDM Clock detection monitor Field Descriptions
        49. 8.5.2.49 REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
          1. Table 130. Revision and PG ID Field Descriptions
        50. 8.5.2.50 I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
          1. Table 131. I2C Checksum Field Descriptions
        51. 8.5.2.51 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
          1. Table 132. Device Book Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Overview
        2. 9.2.2.2 Select Input Capacitance
        3. 9.2.2.3 Select Decoupling Capacitors
        4. 9.2.2.4 Select Bootstrap Capacitors
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Initial Device Configuration - Auto Rate
      2. 9.3.2 Initial Device Configuration - 48 kHz
      3. 9.3.3 Initial Device Configuration - 44.1 kHz
      4. 9.3.4 Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5 Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6 Device Mute
      7. 9.3.7 Device Un-Mute
      8. 9.3.8 Device Sleep
      9. 9.3.9 Device Wake
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YFF|30
  • RJQ|26
订购信息

Battery Tracking Limiter with Brown Out Prevention

The TAS2770 monitors battery voltage (VBAT) and the audio signal to automatically decrease gain when the audio signal peaks exceed a programmable threshold. This helps prevent clipping and extends playback time through end of charge battery conditions. The limiter threshold can be configured to track VBAT below a programmable inflection point with a programmable slope. A minimum threshold sets the limit of threshold reduction from VBAT tracking. Configurable attack rate, hold time and release rate are provided to shape the dynamic response of the limiter (via LIM_ATK_RT[2:0], LIM_HLD_TM[2:0] and LIM_RLS_RT[2:0] register bits).

TAS2770 tas5770l_bop_lim.gifFigure 47. Limiter and Brown Out Prevention Interaction Diagram

A Brown Out Prevention (BOP) feature provides a priority input to the limiter to provide very fast response to transient dips in VBAT at end of charge conditions that can cause system level brown out. When VBAT dips below the BOP threshold, the limiter begins reducing gain with an attack latency of less than 10 µs and a configurable attack rate. When VBAT rises above the BOP threshold, the limiter will begin to release after the programmed hold time.

The limiter is enabled by setting the LIM_EN bit register bit high.

Table 44. Battery Tracking Limiter Enable

LIM_EN Value
0 Disabled (default)
1 Enabled

The limiter has configurable attack rate, hold time and release rate, which are available via the LIM_ATK_RT[2:0], LIM_HLD_TM[2:0] and LIM_RLS_RT[2:0] register bits respectively. The limiter attack and release step size can be set by configuring the LIM_ATK_ST[1:0] and LIM_RLS_ST[1:0] register bits respectively.

Table 45. Limiter Attack Rate

LIM_ATK_RT[2:0] Attack Rate (µs)
0x0 5
0x1 10
0x2 20 (default)
0x3 40
0x4 80
0x5 160
0x6 320
0x7 640

Table 46. Limiter Hold Time

LIM_HLD_TM[2:0] Hold Time (ms)
0x0 0
0x1 10
0x2 25
0x3 50
0x4 100
0x5 250
0x6 500 (default)
0x7 1000

Table 47. Limiter Release Rate

LIM_RLS_RT[2:0] Release Time (ms)
0x0 10
0x1 50
0x2 100
0x3 250
0x4 500
0x5 750
0x6 1000 (default)
0x7 1500

Table 48. Limiter Attack Step Size

LIM_ATK_ST[1:0] Step Size (dB)
00 0.25
01 0.5 (default)
10 1
11 2

Table 49. Limiter Release Step Size

LIM_RLS_ST[1:0] Step Size (dB)
00 0.25
01 0.5 (default)
10 1
11 2

A maximum level of attenuation applied by the limiter and brown out prevention feature is configurable via the LIM_MAX_ATN[4:0] register bits. This attenuation limit is shared between the features. For instance, if the maximum attenuation is set to 6 dB and the limiter has reduced gain by 4 dB, the brown out prevention feature will only be able to reduce the gain further by another 2 dB. If the limiter or brown out prevention feature is attacking and it reaches the maximum attenuation, gain will not be reduced any further.

Table 50. Limiter Max Attenuation

LIM_MAX_ATN[4:0] Attenuation (dB)
0x00 1
0x01 1.5
... ...
0x10 9 (default)
... ...
0x1E 16
0x1F 16.5

The limiter begins reducing gain when the output signal level is greater than the limiter threshold. The limiter can be configured to track VBAT below a programmable inflection point with a minimum threshold value. Figure 48 below shows the limiter configured to limit to a constant level regardless of VBAT level. To achieve this behavior, set the limiter maximum threshold to the desired level via the LIM_TH_MAX[6:0] register bits. Set the limiter inflection point (via the LIM_INF_PT[6:0] register bits) below the minimum allowable VBAT setting. The limiter minimum threshold register bits (LIM_TH_MIN[6:0]) do not impact limiter behavior in this use case.

TAS2770 tas5770l_limiter_fixed.gifFigure 48. Limiter with Fixed Threshold

Table 51. Limiter Maximum Threshold

LIM_TH_MAX[6:0] Threshold (V)
0x00 2
0x01 2.1
... ...
0x6E 13 (default)
... ...
0x7E 14.6
0x7F 14.7

Table 52. Limiter Minimum Threshold

LIM_TH_MIN[6:0] Threshold (V)
0x00 2
0x01 2.1
... ...
0x1E 5 (default)
... ...
0x7E 14.6
0x7F 14.7

Table 53. Limiter Inflection Point

LIM_INF_PT[6:0] Inflection Point (V)
0x00 2
0x01 2.1
... ...
0x58 10.8 (default)
... ...
0x7E 14.6
0x7F 14.7

Figure 49 shows how to configure the limiter to track VBAT below a threshold without a minimum threshold. Set the LIM_TH_MAX[6:0] register bits to the desired threshold and LIM_INF_PT[6:0] register bits to the desired inflection point where the limiter will begin reducing the threshold with VBAT. The LIM_SLOPE[1:0] register bits can be used to change the slope of the limiter tracking with VBAT. The default value of 1 V/V will reduce the threshold 1 V for every 1 V of drop in VBAT. More aggressive tracking slopes can be programmed if desired. Program the LIM_TH_MIN[6:0] below the minimum VBAT to prevent the limiter from having a minimum threshold reduction when tracking VBAT.

TAS2770 tas5770l_limiter_inflection.gifFigure 49. Limiter with Inflection Point

Table 54. Limiter VBAT Tracking Slope

LIM_SLOPE[1:0] Slope (V/V)
00 1 (default)
01 1.5
10 2
11 4

To achieve a limiter that tracks VBAT below a threshold, configure the limiter as explained in the previous example, except program the LIM_TH_MIN[6:0] register bits to the desired minimum threshold. This is shown in Figure 50 below.

TAS2770 tas5770l_limiter_inf_min.gifFigure 50. Limiter with Inflection Point and Minimum Threshold

The TAS2770 also employs a Brown Out Prevention (BOP) feature that serves as a low latency priority input to the limiter engine that begins attacking within 10 µs of VBAT dipping below the programmed BOP threshold. This feature can be enabled by setting the BOP_EN register bit high. It should be noted that the BOP feature is independent of the limiter and will function if enabled even if the limiter is disabled. The BOP threshold is configured by setting the threshold with register bits BOP_TH[7:0].

TAS2770 tas5770l_limiter_block_diagram.gifFigure 51. Limiter Block Diagram

Table 55. Brown Out Prevention Enable

BOP_EN Value
0 Disabled
1 Enabled (default)

Table 56. Brown Out Prevention Threshold

BOP_TH[7:0] Threshold (V)
0x00 4.5
0x01 4.525
0x02 4.55
... ...
0x14 5.0 (default)
... ...
0xFE 10.85
0xFF 10.875

The BOP feature has a separate attack rate, attack step size and hold time from the battery tracking limiter (register bits BOP_ATK_RT[2:0], BOP_ATK_ST[1:0] and BOP_HLD_TM[2:0] respectively). The BOP feature uses the LIM_RLS_RT[2:0] register setting to release after a brown out event.

Table 57. Brown Out Prevention Attack Rate

BOP_ATK_RT[2:0] Attack Rate (µs)
0x0 5
0x1 10
0x2 20 (default)
0x3 40
0x4 80
0x5 160
0x6 320
0x7 640

Table 58. Brown Out Prevention Attack Step Size

BOP_ATK_ST[1:0] Step Size (dB)
00 0.5
01 1 (default)
10 1.5
11 2

Table 59. Brown Out Prevention Hold Time

BOP_HLD_TM[2:0] Hold Time (ms)
0x0 0
0x1 10
0x2 25
0x3 50
0x4 100
0x5 250
0x6 500 (default)
0x7 1000

The TAS2770 can also shutdown the device when a brown out event occurs if the BOP_SHUTDOWN register bit is set high. For the device to continue playing audio again, the device must transition through a SW/HW shutdown state. Setting the BOP_INF_HLD high will cause the limiter to stay in the hold state (i.e. never release) after a cleared brown out event until either the device transitions through a mute or SW/HW shutdown state or the register bit BOP_HLD_CLR is written to a high value (which will cause the device to exit the hold state and begin releasing). This bit is self clearing and will always readback low. Figure 52 below illustrates the entering and exiting from a brown out event.

TAS2770 tas5770l_limiter_bop_active.gifFigure 52. Brown Out Prevention Event

Table 60. Shutdown on Brown Out Event

BOP_SHUTDOWN Value
0 Don't Shutdown (default)
1 Shutdown

Table 61. Infinite Hold on Brown Out Event

BOP_INF_HLD Value
0 Use BOP_HLD_TM after Brown Out event (default)
1 Do not release until BOP_HLD_CLR is asserted high

Table 62. BOP Infinite Hold Clear

BOP_HLD_CLR Value
0 Don't clear (default)
1 Clear event (self clearing)