ZHCSHK8B October   2017  – October 2018 TAS2770

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      功能方框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 PDM Port Timing Requirements
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Mode and Address Selection
      2. 8.3.2 General I2C Operation
      3. 8.3.3 Single-Byte and Multiple-Byte Transfers
      4. 8.3.4 Single-Byte Write
      5. 8.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6 Single-Byte Read
      7. 8.3.7 Multiple-Byte Read
      8. 8.3.8 Register Organization
    4. 8.4 Device Functional Modes
      1. 8.4.1  PDM Input
      2. 8.4.2  TDM Port
      3. 8.4.3  Playback Signal Path
        1. 8.4.3.1 High Pass Filter
        2. 8.4.3.2 Digital Volume Control and Amplifier Output Level
        3. 8.4.3.3 Audio Playback Selection
        4. 8.4.3.4 Battery Tracking Limiter with Brown Out Prevention
        5. 8.4.3.5 Inter Chip Limiter Alignment
          1. 8.4.3.5.1 TDM Mode
        6. 8.4.3.6 Class-D Settings
      4. 8.4.4  SAR ADC
      5. 8.4.5  IV Sense
      6. 8.4.6  Clocks and PLL
      7. 8.4.7  Operational Modes
        1. 8.4.7.1 Hardware Shutdown
        2. 8.4.7.2 Software Shutdown
        3. 8.4.7.3 Mute
        4. 8.4.7.4 Active
        5. 8.4.7.5 Mode Control and Software Reset
      8. 8.4.8  Faults and Status
      9. 8.4.9  Power Sequencing Requirements
      10. 8.4.10 Digital Input Pull Downs
    5. 8.5 Register Maps
      1. 8.5.1 Register Summary Table Book=0x00 Page=0x00
      2. 8.5.2 Register Maps
        1. 8.5.2.1  PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
          1. Table 82. Device Page Field Descriptions
        2. 8.5.2.2  SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
          1. Table 83. Software Reset Field Descriptions
        3. 8.5.2.3  PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
          1. Table 84. Power Control Field Descriptions
        4. 8.5.2.4  PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
          1. Table 85. Playback Configuration 0 Field Descriptions
        5. 8.5.2.5  PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
          1. Table 86. Playback Configuration 1 Field Descriptions
        6. 8.5.2.6  PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
          1. Table 87. Playback Configuration 2 Field Descriptions
        7. 8.5.2.7  PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
          1. Table 88. Playback Configuration 3 Field Descriptions
        8. 8.5.2.8  MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
          1. Table 89. Misc Configuration Field Descriptions
        9. 8.5.2.9  PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
          1. Table 90. PDM Input Register 0 Field Descriptions
        10. 8.5.2.10 PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
          1. Table 91. PDM Configuration 1 Field Descriptions
        11. 8.5.2.11 TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
          1. Table 92. TDM Configuration 0 Field Descriptions
        12. 8.5.2.12 TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
          1. Table 93. TDM Configuration 1 Field Descriptions
        13. 8.5.2.13 TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
          1. Table 94. TDM Configuration 2 Field Descriptions
        14. 8.5.2.14 TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
          1. Table 95. TDM Configuration 3 Field Descriptions
        15. 8.5.2.15 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
          1. Table 96. TDM Configuration 4 Field Descriptions
        16. 8.5.2.16 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
          1. Table 97. TDM Configuration 5 Field Descriptions
        17. 8.5.2.17 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
          1. Table 98. TDM Configuration 6 Field Descriptions
        18. 8.5.2.18 TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
          1. Table 99. TDM Configuration 7 Field Descriptions
        19. 8.5.2.19 TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
          1. Table 100. TDM Configuration 8 Field Descriptions
        20. 8.5.2.20 TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
          1. Table 101. TDM Configuration 9 Field Descriptions
        21. 8.5.2.21 TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
          1. Table 102. TDM Configuration 10 Field Descriptions
        22. 8.5.2.22 LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
          1. Table 103. Limiter Configuration 0 Field Descriptions
        23. 8.5.2.23 LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
          1. Table 104. Limiter Configuration 1 Field Descriptions
        24. 8.5.2.24 LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
          1. Table 105. Limiter Configuration 2 Field Descriptions
        25. 8.5.2.25 LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
          1. Table 106. Limiter Configuration 3 Field Descriptions
        26. 8.5.2.26 LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
          1. Table 107. Limiter Configuration 4 Field Descriptions
        27. 8.5.2.27 LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
          1. Table 108. Limiter Configuration 5 Field Descriptions
        28. 8.5.2.28 BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
          1. Table 109. Brown Out Prevention 0 Field Descriptions
        29. 8.5.2.29 BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
          1. Table 110. Brown Out Prevention 1 Field Descriptions
        30. 8.5.2.30 BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
          1. Table 111. Brown Out Prevention 2 Field Descriptions
        31. 8.5.2.31 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
          1. Table 112. Inter Chip Limiter Alignment 0 Field Descriptions
        32. 8.5.2.32 ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
          1. Table 113. Inter Chip Limiter Alignment 1 Field Descriptions
        33. 8.5.2.33 INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
          1. Table 114. Interrupt Mask 0 Field Descriptions
        34. 8.5.2.34 INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
          1. Table 115. Interrupt Mask 1 Field Descriptions
        35. 8.5.2.35 INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
          1. Table 116. Live Interrupt Readback 0 Field Descriptions
        36. 8.5.2.36 INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
          1. Table 117. Live Interrupt Readback 1 Field Descriptions
        37. 8.5.2.37 INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
          1. Table 118. Latched Interrupt Readback 0 Field Descriptions
        38. 8.5.2.38 INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
          1. Table 119. Latched Interrupt Readback 1 Field Descriptions
        39. 8.5.2.39 INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
          1. Table 1.   INT_LTCH2 Register Address: 0x26
          2. Table 120. INT_LTCH2 Field Descriptions
        40. 8.5.2.40 VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
          1. Table 121. SAR ADC Conversion 0 Field Descriptions
        41. 8.5.2.41 VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
          1. Table 122. SAR ADC Conversion 1 Field Descriptions
        42. 8.5.2.42 TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
          1. Table 123. SAR ADC Conversion 2 Field Descriptions
        43. 8.5.2.43 TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
          1. Table 124. SAR ADC Conversion 2 Field Descriptions
        44. 8.5.2.44 INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
          1. Table 125. Interrupt Configuration Field Descriptions
        45. 8.5.2.45 DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
          1. Table 126. Digital Input Pin Pull Down Field Descriptions
        46. 8.5.2.46 MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
          1. Table 127. Misc Configuration Field Descriptions
        47. 8.5.2.47 CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
          1. Table 128. Clock Configuration Field Descriptions
        48. 8.5.2.48 TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
          1. Table 129. TDM Clock detection monitor Field Descriptions
        49. 8.5.2.49 REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
          1. Table 130. Revision and PG ID Field Descriptions
        50. 8.5.2.50 I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
          1. Table 131. I2C Checksum Field Descriptions
        51. 8.5.2.51 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
          1. Table 132. Device Book Field Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Overview
        2. 9.2.2.2 Select Input Capacitance
        3. 9.2.2.3 Select Decoupling Capacitors
        4. 9.2.2.4 Select Bootstrap Capacitors
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Initial Device Configuration - Auto Rate
      2. 9.3.2 Initial Device Configuration - 48 kHz
      3. 9.3.3 Initial Device Configuration - 44.1 kHz
      4. 9.3.4 Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5 Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6 Device Mute
      7. 9.3.7 Device Un-Mute
      8. 9.3.8 Device Sleep
      9. 9.3.9 Device Wake
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YFF|30
  • RJQ|26
订购信息

Electrical Characteristics

TA = 25 °C, VBAT = 12.6 V, AVDD = IOVDD = 1.8 V, RL = 4 Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 21 dBV, SDZ = 1, Measured filter free using Parameter Measurement Information (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT and OUTPUT
VIH High-level digital input logic voltage threshold All digital pins except SDA and SCL; IOVDD = 1.8 V. 0.65 × IOVDD V
VIL Low-level digital input logic voltage threshold All digital pins except SDA and SCL; IOVDD = 1.8 V. 0.35 × IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL; IOVDD = 1.8 V. 0.7 x IOVDD V
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL; IOVDD = 1.8 V. 0.3 x IOVDD V
VOH High-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOVDD = 1.8 V; IOH = 2 mA. IOVDD – 0.45 V V
VOL Low-level digital output voltage All digital pins except SDA, SCL and IRQZ; IOVDD = 1.8 V; IOL = –2 mA. 0.45 V
VOL(I2C) Low-level digital output voltage SDA and SCL; IOVDD = 1.8 V; IOL(I2C) = –2 mA. 0.2 x IOVDD V
VOL(IRQZ) Low-level digital output voltage for IRQZ open drain Output IRQZ; IOVDD = 1.8 V; IOL(IRQZ) = –2 mA. 0.45 V
IIH Input logic-high leakage for digital inputs All digital pins; Input = IOVDD. –5 0.1 5 µA
IIL Input logic-low leakage for digital inputs All digital pins; Input = GND. –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pull down resistance for digital input/IO pins when asserted on SDOUT, SDIN, FSYNC, SBCLK, PDMD, PDMCK 18
TDM SERIAL AUDIO PORT
PCM Sample Rates & FSYNC Input Frequency Single Speed, I2S/TDM Operation 48 kHz
Double Speed, I2S/TDM Operation 96
Quadruple Speed, I2S/TDM Operation 192
SBCLK Input Frequency I2S/TDM Operation 2.54 27.1 MHz
SBCLK Maximum Input Jitter RMS Jitter below 40 kHz that can be tolerated without performance degradation 1 ns
RMS Jitter above 40 kHz that can be tolerated without performance degradation 10
SBCLK Cycles per FSYNC in I2S and TDM Modes Values: 64, 96, 128, 192, 256, 384 and 512 64 512 Cycles
PDM AUDIO PORT
PDM clock input frequency Single Rate PDM 3.072 MHz
Double Rate PDM 6.144
PDM sensor clock rate to PCM sample rate oversampling ratios Single Speed PCM. Values: 64X and 128X. 64 128
Double Speed PCM. Values: 32X and 64X. 32 64
Quadruple Speed PCM. Values: 16X and 32X. 16 32
PROTECTION CIRCUITRY
Thermal shutdown temperature 140 °C
Thermal shutdown retry 1.5 s
VBAT undervoltage lockout threshold (UVLO) UVLO is asserted 4 V
VBAT overvoltage lockout threshold (OVLO) OVLO is asserted 18 V
AMPLIFIER PERFORMANCE
POUT Maximum Continuous Output Power 0.1% THD+N RL = 8 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 8.4 V 3.7 W
RL = 4 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 8.4 V 6.6
RL = 8 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 12.6 V 8.5
RL = 4 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 12.6 V 14.2
Maximum Continuous Output Power 1% THD+N RL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 8.4 V 4
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 8.4 V 7.1
RL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 12.6 V 9.1
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 12.6 V 15.4
System efficiency at POUT = 1 W RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 8.4 V 89 %
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 8.4 V 84 %
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 12.6 V 87.5 %
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 12.6 V 82.7 %
System efficiency at 0.1% THD+N power level RL = 8 Ω + 33 µH, POUT = 3.7W, fin = 1 kHz, VBAT = 8.4 V 92 %
RL = 4 Ω + 33 µH, POUT = 6.6 W, fin = 1 kHz, VBAT = 8.4 V 87 %
RL = 8 Ω + 33 µH, POUT = 8.5 W, fin = 1 kHz, VBAT = 12.6 V 92 %
RL = 4 Ω + 33 µH, POUT = 14.2 W, fin = 1 kHz, VBAT = 12.6 V 86 %
THD+N Total harmonic distortion + noise POUT = 1 W, RL = 8 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 8.4 V 0.01 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 8.4 V 0.01 %
POUT = 1 W, RL = 8 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 12.6 V 0.01 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 12.6 V 0.01 %
VN Idle channel noise A-Weighted, 20 Hz - 20 kHz, DAC Modulator Running 31 µV
VBAT = 8.4 V 32 µV
VBAT = 12.6 V 36 µV
FPWM Class-D PWM switching frequency Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0 384 kHz
Fixed Frequency Mode, CLASSD_SYNC=0 345.6 384 422.4
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1, 88.2, 174.6 kHz 44.1·8
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48, 96, 192 kHz 48·8
VOS Output offset voltage -1 1 mV
DNR Dynamic range A-Weighted, -60 dBFS Method 108 dB
SNR Signal to noise ratio A-Weighted, Referenced to 1 % THD+N Output Level 108 dB
KCP Click and pop performance Into and out of Mute, Shutdown, Power Up, Power Down and audio clocks starting and stopping. A-weighted 5 mV
Programmable output level range 12.5 21 dBV
Programmable output level step size 0.5 dB
AVERROR Amplifier gain error POUT=1W ±0.1 dB
ARIPPLE Frequency response passband ripple 20 Hz - 20 kHz ±0.1 dB
Mute attenuation Device in Shutdown or Muted in Normal Operation 110 dB
Output short circuit limit VBAT = 12.6 V, Output to Output, Output to GND or Output to VBAT Short 6 A
RDS(ON)FET Power stage on-resistance (high-side + low-side + sense resistor) TA = 25 °C 510
VBAT power-supply rejection ratio VBAT = 12.6 V + 200 mVpp, fripple = 217 Hz 105 dB
VBAT = 12.6 V + 200 mVpp, fripple = 20 kHz 86
AVDD power-supply rejection ratio AVDD = 1.8 V + 200 mVpp, fripple = 217 Hz 95 dB
AVDD = 1.8 V + 200 mVpp, fripple = 20 kHz 88
Turn on time from release of SW shutdown No Volume Ramping 1.2 ms
Volume Ramping 5.3
Turn off time from assertion of SW shutdown to amp Hi-Z No Volume Ramping 0.3 ms
Volume Ramping 4.7
PCM PLAYBACK CHARACTERISTICS
Playback latency from latched input sample to speaker terminals Single Speed, I2S/TDM 3.5 samples
Double Speed, I2S/TDM 3.5
Quadruple Speed, I2S/TDM 3.5
Playback –0.1 dB bandwidth Single Speed, I2S/TDM 23.06 kHz
Double Speed, I2S/TDM 21.79
Quadruple Speed, I2S/TDM 21.69
Playback –3 dB bandwidth Single Speed, I2S/TDM 24 kHz
Double Speed, I2S/TDM 23
Quadruple Speed, I2S/TDM 27.26
PDM PLAYBACK CHARACTERISTICS
Playback latency from latched data bit to speaker terminals Single Rate PDM, PDMD input 7.07 µs
Double Rate PDM, PDMD input 5.02
Playback –0.1 dB bandwidth Single Rate PDM, PDMD input 41.5 kHz
Double Rate PDM, PDMD input 88
Playback –3 dB bandwidth Single Rate PDM, PDMD input 77.5 kHz
Double Rate PDM, PDMD input 143
SPEAKER CURRENT SENSE
DNR Dynamic range Un-Weighted, Relative to 0 dBFS 69 dB
THD+N Total harmonic distortion + noise RL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 5 W –60 dB
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 7.5 W –60
Full-scale input current 3.75 A
Current-sense accuracy RL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W) ±1 %
Current-sense gain error over temperature –20°C to 70°C, POUT = 1 W ±0.75%
Current-sense gain error over output power 50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone ±0.75%
Current-sense frequency response Max deviation above and below passband gain ±0.2 dB
SPEAKER VOLTAGE SENSE
DNR Dynamic range Un-Weighted, Relative 0 dBFS 69 dB
THD+N Total harmonic distortion + noise RL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 5 W –60 dB
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 7.5 W –60
Full-scale input voltage 14 VPK
Voltage-sense accuracy RL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W) ±1%
Voltage-sense gain error over temperature –20°C to 70°C, POUT = 1 W ±0.75%
Voltage-sense gain error over output power 50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone ±0.75%
Voltage-sense frequency response Max deviation above and below passband gain ±0.2 dB
SPEAKER VOLTAGE/CURRENT SENSE RATIO
Gain ratio error over output power 50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone ±0.75%
Gain ratio error over temperature –20°C to 70°C ±0.5%
TYPICAL CURRENT CONSUMPTION
Current consumption in hardware shutdown SDZ = 0, VBAT 0.1 µA
SDZ = 0, AVDD 1
SDZ = 0, IOVDD 0.1
Current consumption in software shutdown All Clocks Stopped, VBAT 10 µA
All Clocks Stopped, AVDD 10
All Clocks Stopped, IOVDD 1
Current consumption during active operation with IV sense disabled fs = 48 kHz, VBAT 3.1 mA
fs = 48 kHz, AVDD 10
fs = 48 kHz, IOVDD 0.1
Current consumption during active operation with IV sense enabled fs = 48 kHz, VBAT 3.1 mA
fs = 48 kHz, AVDD 12.5
fs = 48 kHz, IOVDD 0.1
PEAK VOLTAGE LIMITER
Limiter maximum threshold 2 14.7 V
Limiter minimum threshold 2 14.7 V
Limiter inflection point 2 14.7 V
Limiter VBAT tracking slope 1 4 V/V
Limiter max attenuation 1 16.5 dB
Limiter latency Time from VBAT dipping below threshold to initial gain reduction 23 µs
Limiter attack rate 5 640 µs/step
Limiter attack step size 0.25 2 dB/step
Limiter hold time 0 1000 ms
Limiter release rate 10 1500 ms/step
Limiter release step size 0.25 2 dB/step
BROWN OUT PREVENTION LIMITER
Brownout prevention threshold 4.5 10.875 V
Brownout prevention threshold step size 25 mV
Brownout prevention threshold tolerance Measured at VBAT of 5V and 10V ±25 mV
Brownout prevention latency Time from VBAT dipping below threshold to initial gain reduction 20 µs
Brownout prevention attack rate 5 640 µs/step
Brownout prevention attack step size 0.5 2 dB/step
Brownout prevention hold time 0 1000 ms
Brownout prevention release rate 10 1500 ms/step
Brownout prevention release step size 0.25 2 dB/step