ZHCSFP7A November   2016  – February 2017 TAS2557

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. 说明(续)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  I2C Timing Requirements
    7. 8.7  SPI Timing Requirements
    8. 8.8  I2S/LJF/RJF Timing in Master Mode
    9. 8.9  I2S/LJF/RJF Timing in Slave Mode
    10. 8.10 DSP Timing in Master Mode
    11. 8.11 DSP Timing in Slave Mode
    12. 8.12 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  General I2C Operation
      2. 10.3.2  Single-Byte and Multiple-Byte Transfers
      3. 10.3.3  Single-Byte Write
      4. 10.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 10.3.5  Single-Byte Read
      6. 10.3.6  Multiple-Byte Read
      7. 10.3.7  General SPI Operation
      8. 10.3.8  Class-D Edge Rate Control
      9. 10.3.9  IV Sense
      10. 10.3.10 Battery Tracking AGC
      11. 10.3.11 Boost Control
        1. 10.3.11.1 Boost Mode
        2. 10.3.11.2 Configurable Boost Current Limit (ILIM)
      12. 10.3.12 Thermal Fold-back
      13. 10.3.13 Fault Protection
        1. 10.3.13.1 Speaker Over-Current
        2. 10.3.13.2 Analog Under-Voltage
        3. 10.3.13.3 Die Over-Temperature
        4. 10.3.13.4 Clocking Faults
      14. 10.3.14 Brownout
      15. 10.3.15 Spread Spectrum vs Synchronized
      16. 10.3.16 IRQs and Flags
      17. 10.3.17 Software Reset
      18. 10.3.18 PurePath Console 3 Software TAS2557 Application
    4. 10.4 Device Functional Modes
      1. 10.4.1 Audio Digital I/O Interface
        1. 10.4.1.1 I2S Mode
        2. 10.4.1.2 DSP Mode
        3. 10.4.1.3 Right-Justified Mode (RJF)
        4. 10.4.1.4 Left-Justified Mode (LJF)
      2. 10.4.2 Mono PCM Mode
      3. 10.4.3 Stereo Application Example - TDM Mode
    5. 10.5 Operational Modes
      1. 10.5.1 Hardware Shutdown
      2. 10.5.2 Software Shutdown
      3. 10.5.3 Low Power Sleep
      4. 10.5.4 Software Reset
      5. 10.5.5 Device Processing Modes
        1. 10.5.5.1 Mode 1 - PCM input playback only
        2. 10.5.5.2 Mode 2 - PCM input playback + PCM IVsense output
        3. 10.5.5.3 Mode 3 - Smart Amp Mode
    6. 10.6 Programming
      1. 10.6.1 Code Loading and CRC check
      2. 10.6.2 Device Power Up and Unmute Sequence
      3. 10.6.3 Device Mute and Power Down Sequence
  11. 11Applications and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Detailed Design Procedure
          1. 11.2.1.1.1 Mono/Stereo Configuration
          2. 11.2.1.1.2 Boost Converter Passive Devices
          3. 11.2.1.1.3 EMI Passive Devices
          4. 11.2.1.1.4 Miscellaneous Passive Devices
      2. 11.2.2 Application Performance Plots
    3. 11.3 Initialization Set Up
  12. 12Power Supply Recommendations
    1. 12.1 Power Supplies
    2. 12.2 Power Supply Sequencing
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Register Map
    1. 14.1 Register Map Summary
      1. 14.1.1 Register Summary Table Book=0x00 Page=0x00
      2. 14.1.2 Register Summary Table Book=0x00 Page=0x01
      3. 14.1.3 Register Summary Table Book=0x00 Page=0x02
    2. 14.2 Register Maps
      1. 14.2.1   PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
      2. 14.2.2   RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
      3. 14.2.3   POWER_1 (book=0x00 page=0x00 address=0x04) [reset=0h]
      4. 14.2.4   POWER_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
      5. 14.2.5   SPK_GAIN_EDGE (book=0x00 page=0x00 address=0x06) [reset=0h]
      6. 14.2.6   MUTE (book=0x00 page=0x00 address=0x07) [reset=0h]
      7. 14.2.7   SNS_CTRL (book=0x00 page=0x00 address=0x08) [reset=0h]
      8. 14.2.8   BOOST_CTRL_1 (book=0x00 page=0x00 address=0x09) [reset=0h]
      9. 14.2.9   SAR_CTRL_2 (book=0x00 page=0x00 address=0x14) [reset=32h]
      10. 14.2.10  SAR_CTRL_3 (book=0x00 page=0x00 address=0x15) [reset=4h]
      11. 14.2.11  SAR_VBAT_MSB (book=0x00 page=0x00 address=0x16) [reset=0h]
      12. 14.2.12  SAR_VBAT_LSB (book=0x00 page=0x00 address=0x17) [reset=0h]
      13. 14.2.13  SAR_VBST_MSB (book=0x00 page=0x00 address=0x18) [reset=0h]
      14. 14.2.14  SAR_VBST_LSB (book=0x00 page=0x00 address=0x19) [reset=0h]
      15. 14.2.15  SAR_TMP1_MSB (book=0x00 page=0x00 address=0x1A) [reset=0h]
      16. 14.2.16  SAR_TMP1_LSB (book=0x00 page=0x00 address=0x1B) [reset=0h]
      17. 14.2.17  SAR_TMP2_MSB (book=0x00 page=0x00 address=0x1C) [reset=0h]
      18. 14.2.18  SAR_TMP2_LSB (book=0x00 page=0x00 address=0x1D) [reset=0h]
      19. 14.2.19  CRC_CHECKSUM (book=0x00 page=0x00 address=0x20) [reset=0h]
      20. 14.2.20  CRC_RESET (book=0x00 page=0x00 address=0x21) [reset=0h]
      21. 14.2.21  DSP_CTRL (book=0x00 page=0x00 address=0x22) [reset=1h]
      22. 14.2.22  SSM_CTRL (book=0x00 page=0x00 address=0x28) [reset=0h]
      23. 14.2.23  ASI_CTRL_1 (book=0x00 page=0x00 address=0x2A) [reset=0h]
      24. 14.2.24  BOOST_CTRL_2 (book=0x00 page=0x00 address=0x2B) [reset=3h]
      25. 14.2.25  CLOCK_CTRL_1 (book=0x00 page=0x00 address=0x2C) [reset=0h]
      26. 14.2.26  CLOCK_CTRL_2 (book=0x00 page=0x00 address=0x2D) [reset=17h]
      27. 14.2.27  CLOCK_CTRL_3 (book=0x00 page=0x00 address=0x2E) [reset=0h]
      28. 14.2.28  ASI_CTRL_2 (book=0x00 page=0x00 address=0x2F) [reset=0h]
      29. 14.2.29  CLOCK_CTRL_4 (book=0x00 page=0x00 address=0x32) [reset=0h]
      30. 14.2.30  DEBUG_1 (book=0x00 page=0x00 address=0x35) [reset=0h]
      31. 14.2.31  POWER_STATUS (book=0x00 page=0x00 address=0x64) [reset=0h]
      32. 14.2.32  DSP_BOOT_STATUS (book=0x00 page=0x00 address=0x65) [reset=0h]
      33. 14.2.33  INT_DET_1 (book=0x00 page=0x00 address=0x68) [reset=0h]
      34. 14.2.34  INT_DET_2 (book=0x00 page=0x00 address=0x6C) [reset=0h]
      35. 14.2.35  LOW_POWER (book=0x00 page=0x00 address=0x79) [reset=0h]
      36. 14.2.36  BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
      37. 14.2.37  PAGE (book=0x00 page=0x01 address=0x00) [reset=1h]
      38. 14.2.38  ASI1_FORMAT (book=0x00 page=0x01 address=0x01) [reset=10h]
      39. 14.2.39  ASI1_OFFSET_1 (book=0x00 page=0x01 address=0x03) [reset=0h]
      40. 14.2.40  ASI1_BUSKEEP (book=0x00 page=0x01 address=0x05) [reset=0h]
      41. 14.2.41  ASI1_BCLK (book=0x00 page=0x01 address=0x08) [reset=0h]
      42. 14.2.42  ASI1_WCLK (book=0x00 page=0x01 address=0x09) [reset=8h]
      43. 14.2.43  ASI1_DIN_DOUT (book=0x00 page=0x01 address=0x0C) [reset=0h]
      44. 14.2.44  ASI1_BDIV_CLK (book=0x00 page=0x01 address=0x0D) [reset=1h]
      45. 14.2.45  ASI1_BDIV_RATIO (book=0x00 page=0x01 address=0x0E) [reset=2h]
      46. 14.2.46  ASI1_WDIV_RATIO (book=0x00 page=0x01 address=0x0F) [reset=20h]
      47. 14.2.47  ASI1_CLK_OUT (book=0x00 page=0x01 address=0x10) [reset=0h]
      48. 14.2.48  ASI2_FORMAT (book=0x00 page=0x01 address=0x15) [reset=10h]
      49. 14.2.49  ASI2_OFFSET_1 (book=0x00 page=0x01 address=0x17) [reset=0h]
      50. 14.2.50  ASI2_BUSKEEP (book=0x00 page=0x01 address=0x19) [reset=0h]
      51. 14.2.51  ASI2_BCLK (book=0x00 page=0x01 address=0x1C) [reset=20h]
      52. 14.2.52  ASI2_WCLK (book=0x00 page=0x01 address=0x1D) [reset=28h]
      53. 14.2.53  ASI2_DIN_DOUT (book=0x00 page=0x01 address=0x20) [reset=38h]
      54. 14.2.54  ASI2_BDIV_CLK (book=0x00 page=0x01 address=0x21) [reset=1h]
      55. 14.2.55  ASI2_BDIV_RATIO (book=0x00 page=0x01 address=0x22) [reset=2h]
      56. 14.2.56  ASI2_WDIV_RATIO (book=0x00 page=0x01 address=0x23) [reset=20h]
      57. 14.2.57  ASI2_CLK_OUT (book=0x00 page=0x01 address=0x24) [reset=33h]
      58. 14.2.58  GPIO1_PIN (book=0x00 page=0x01 address=0x3D) [reset=1h]
      59. 14.2.59  GPIO2_PIN (book=0x00 page=0x01 address=0x3E) [reset=1h]
      60. 14.2.60  GPIO3_PIN (book=0x00 page=0x01 address=0x3F) [reset=10h]
      61. 14.2.61  GPIO4_PIN (book=0x00 page=0x01 address=0x40) [reset=7h]
      62. 14.2.62  GPIO5_PIN (book=0x00 page=0x01 address=0x41) [reset=0h]
      63. 14.2.63  GPIO6_PIN (book=0x00 page=0x01 address=0x42) [reset=0h]
      64. 14.2.64  GPIO7_PIN (book=0x00 page=0x01 address=0x43) [reset=0h]
      65. 14.2.65  GPIO8_PIN (book=0x00 page=0x01 address=0x44) [reset=0h]
      66. 14.2.66  GPIO9_PIN (book=0x00 page=0x01 address=0x45) [reset=0h]
      67. 14.2.67  GPIO10_PIN (book=0x00 page=0x01 address=0x46) [reset=0h]
      68. 14.2.68  GPI_PIN (book=0x00 page=0x01 address=0x4D) [reset=0h]
      69. 14.2.69  GPIO_HIZ_1 (book=0x00 page=0x01 address=0x4F) [reset=0h]
      70. 14.2.70  GPIO_HIZ_2 (book=0x00 page=0x01 address=0x50) [reset=0h]
      71. 14.2.71  GPIO_HIZ_3 (book=0x00 page=0x01 address=0x51) [reset=0h]
      72. 14.2.72  GPIO_HIZ_4 (book=0x00 page=0x01 address=0x52) [reset=0h]
      73. 14.2.73  GPIO_HIZ_5 (book=0x00 page=0x01 address=0x53) [reset=0h]
      74. 14.2.74  BIT_BANG_OUT1 (book=0x00 page=0x01 address=0x58) [reset=0h]
      75. 14.2.75  BIT_BANG_OUT2 (book=0x00 page=0x01 address=0x59) [reset=0h]
      76. 14.2.76  BIT_BANG_IN1 (book=0x00 page=0x01 address=0x5A) [reset=0h]
      77. 14.2.77  BIT_BANG_IN2 (book=0x00 page=0x01 address=0x5B) [reset=0h]
      78. 14.2.78  BIT_BANG_IN3 (book=0x00 page=0x01 address=0x5C) [reset=0h]
      79. 14.2.79  ASIM_BUSKEEP (book=0x00 page=0x01 address=0x60) [reset=0h]
      80. 14.2.80  ASIM_MODE (book=0x00 page=0x01 address=0x61) [reset=8h]
      81. 14.2.81  ASIM_NUM_DEV (book=0x00 page=0x01 address=0x62) [reset=0h]
      82. 14.2.82  ASIM_FORMAT (book=0x00 page=0x01 address=0x63) [reset=10h]
      83. 14.2.83  ASIM_BDIV_CLK (book=0x00 page=0x01 address=0x64) [reset=1h]
      84. 14.2.84  ASIM_BDIV_RATIO (book=0x00 page=0x01 address=0x65) [reset=2h]
      85. 14.2.85  ASIM_WDIV_RATIO_1 (book=0x00 page=0x01 address=0x66) [reset=0h]
      86. 14.2.86  ASIM_WDIV_RATIO_2 (book=0x00 page=0x01 address=0x67) [reset=20h]
      87. 14.2.87  ASIM_BCLK (book=0x00 page=0x01 address=0x68) [reset=40h]
      88. 14.2.88  ASIM_WCLK (book=0x00 page=0x01 address=0x69) [reset=38h]
      89. 14.2.89  ASIM_DIN (book=0x00 page=0x01 address=0x6A) [reset=70h]
      90. 14.2.90  INT_GEN_1 (book=0x00 page=0x01 address=0x6C) [reset=0h]
      91. 14.2.91  INT_GEN_2 (book=0x00 page=0x01 address=0x6D) [reset=0h]
      92. 14.2.92  INT_GEN_3 (book=0x00 page=0x01 address=0x6E) [reset=0h]
      93. 14.2.93  INT_GEN_4 (book=0x00 page=0x01 address=0x6F) [reset=0h]
      94. 14.2.94  INT_GEN_5 (book=0x00 page=0x01 address=0x70) [reset=0h]
      95. 14.2.95  INT_GEN_6 (book=0x00 page=0x01 address=0x71) [reset=0h]
      96. 14.2.96  INT_IND_MODE (book=0x00 page=0x01 address=0x72) [reset=0h]
      97. 14.2.97  MAIN_CLK_PIN (book=0x00 page=0x01 address=0x73) [reset=Dh]
      98. 14.2.98  PLL_CLK_PIN (book=0x00 page=0x01 address=0x74) [reset=Dh]
      99. 14.2.99  CLKOUT_MUX (book=0x00 page=0x01 address=0x75) [reset=Dh]
      100. 14.2.100 CLKOUT_CDIV_RATIO (book=0x00 page=0x01 address=0x76) [reset=1h]
      101. 14.2.101 I2C_MISC (book=0x00 page=0x01 address=0x7C) [reset=0h]
      102. 14.2.102 DEVICE_ID (book=0x00 page=0x01 address=0x7D) [reset=12h]
      103. 14.2.103 PAGE (book=0x00 page=0x02 address=0x00) [reset=1h]
      104. 14.2.104 RAMP_CTRL (book=0x00 page=0x02 address=0x06) [reset=0h]
      105. 14.2.105 PROTECTION_CFG (book=0x00 page=0x02 address=0x09) [reset=3h]
  15. 15器件和文档支持
    1. 15.1 文档支持
    2. 15.2 社区资源
    3. 15.3 商标
    4. 15.4 静电放电警告
    5. 15.5 Glossary
  16. 16机械、封装和可订购信息
    1. 16.1 封装尺寸

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YZ|42
订购信息

Specifications

Absolute Maximum Ratings

Over operating free-air temperature range, TA = 25°C (unless otherwise noted)(1)
MIN MAX UNIT
Battery Voltage VBAT –0.3 6 V
Analog Supply Voltage AVDD –0.3 2 V
Digital Supply Voltage DVDD –0.3 2 V
I/O Supply Voltage IOVDD –0.3 3.9 V
Digital Input Voltage –0.3 IOVDD + 0.3 V
Output Continuous Total Power Dissipation See Thermal Information NA
Storage Temperature, Tstg –65 150 °C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Procedures is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic Discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Battery Voltage VBAT 2.9(1) 3.6 5.5 V
Analog Supply Voltage AVDD 1.65 1.8 1.95 V
Digital Supply Voltage DVDD 1.65 1.8 1.95 V
I/O Supply Voltage 1.8V IOVDD 1.62 1.8 1.98 V
I/O Supply Voltage 3.3V IOVDD 3.0 3.3 3.6 V
TA Operating Free-Air Temperature –40 85 °C
TJ Operating Junction Temperature –40 150 °C
Device is functional down to 2.7V. See Battery Tracking AGC

Thermal Information

THERMAL METRIC(1) TAS2557 UNIT
42 PINS
RθJA Junction to Ambient Thermal Resistance 49.8 °C/W
RθJC(top) Junction to Case (top) Thermal Resistance 0.2
RθJB Junction to Board Thermal Resistance 7.1
ψJT Junction to Top Characterization Parameter 0.8
ψJB Junction to Board Characterization Parameter 7.1
RθJC(bot) Junction to Case (bottom) Thermal Resistance n/a
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Electrical Characteristics

VBAT = 3.6V, AVDD = DVDD = IOVDD = 1.8 V, RESET = IOVDD, Gain = 16.4 dB, ERC = 14ns, Boost Inductor = 2.2 µH, RL = 8 Ω + 33 µH, 1-kHz input frequency, 48- kHz sample rate for digital input, Class-H Boost Enabled, TA= 25°C, ILIM = 3 A (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BOOST CONVERTER
Boost Output Voltage Average voltage (w/o including ripple) 8.5 V
Boost Converter Switching Frequency 1.77 MHz
Boost Converter Current Limit 3 A
Boost Converter Max In-Rush Current High Efficiency Mode: Max inductor inrush and startup current after enable 4 A
Normal Efficiency Mode: Max inductor inrush and startup current after enable 1.5
CLASS-D CHANNEL
Output Voltage for Full-Scale Digital Input 6.6 VRMS
Load Resistance (Load Spec Resistance) 3.6 8 Ω
Class-D Frequency Avg Frequency in Spread-Spectrum Mode 384 kHz
Fixed Frequency 44.1 × 8 48 × 8
Class-D + Boost Efficiency POUT = 3.5 W (sinewave) ROM Mode 1 80 %
POUT = 0.5 W (sinewave) ROM Mode 1 87
Class-D Output Current Limit (Short Circuit Protection) VBOOST = 8.5 V, OUT– shorted to VBAT, VBOOST, GND 6 A
Class-D Output Offset Voltage in Digital Input Mode –2.5 2.5 mV
Programmable Channel Gain Accuracy ±0.5 dB
Mute Attenuation Device in shutdown or device in normal operation and muted 150 dB
VBAT Power Supply Rejection Ratio (PSRR) Ripple of 200 mVpp at 217 Hz 110 dB
AVDD Power Supply Rejection Ratio (PSRR) Ripple of 200 mVpp at 217 Hz 99 dB
THD+N 1 kHz, POUT = 0.1W 0.0041 %
1 kHz, Po = 0.5W 0.0036
1 kHz, Po = 1 W 0.0035
1 kHz, Po = 3 W 0.02
Output Integrated Noise (20Hz-20kHz) - 8 Ω A-weighted filter, DAC modulator switching 15.9 µV
Signal-to-Noise Ratio Referenced to 1% THD+N at output, A-weighted 110.6 dB
Max Output Power, 3-A Current Limit THD+N=1%, 8-Ω Load 3.7 W
THD+N=1%, 6-Ω Load 4.5
THD+N=1%, 4-Ω Load 5
Startup Pop Digital Input, A-weighted output 10 mV
Output Impedance in Shutdown /RESET = 0 V 10
Startup Time Time taken from end of configuring device in ROM mode1/2 to speaker output signal in SPI mode running at 25 MHz with 48 ksps input 8 mS
Shutdown Time Measured from time when device is programmed in software shutdown mode 100 µS
CURRENT SENSE
Current Sense Full Scale Peak current which will give full scale digital output 8-Ω load 1.25 APEAK
Peak current which will give full scale digital output 6-Ω load 1.48
Peak current which will give full scale digital output 4-Ω load 1.76
Current Sense Accuracy IOUT = 354 mARMS (1 W) 1 %
VOLTAGE SENSE
Voltage Sense Full Scale Peak voltage which will give full scale digital output 9.353 VPEAK
Voltage Sense Accuracy VOUT = 2.83 Vrms (1 W) 1 %
INTERFACE
Voltage and Current Sense Data Rate TDM/I2S 48 kHz
Voltage and Current Sense ADC OSR TDM/I2S 64 OSR
FMCLK MCLK frequency 0.512 49.15 MHz
POWER CONSUMPTION
Power Consumption with Digital Input and Speaker Protection Disabled (ROM MODE 1) From VBAT, PLL on, no signal 3 mA
From AVDD, PLL on, no signal 3 mA
From DVDD, PLL on, no signal 7.2 mA
Power Consumption with Digital Input and Speaker Protection Enabled From VBAT, PLL on, no signal 4 mA
From AVDD, PLL on, no signal 5.1 mA
From DVDD, PLL on, no signal 22 mA
Power Consumption in Hardware Shutdown From VBAT, /RESET = 0 0.1 µA
From AVDD, /RESET = 0 0.2 µA
From DVDD, /RESET = 0 2 µA
Power Consumption in Software Shutdown See Low Power Sleep From VBAT 0.1 µA
From AVDD 0.1 µA
From DVDD 9.7 µA
DIGITAL INPUT / OUTPUT
VIH High-Level Digital Input Voltage All digital pins except SDA and SCL, IOVDD = 1.8-V operation 0.65 × IOVDD V
VIL Low-Level Digital input Voltage 0.35 × IOVDD V
VIH High-Level Digital Input Voltage All digital pins except SDA and SCL, IOVDD = 3.3-V operation 2 V
VIL Low-Level Ddigital Input Voltage 0.45 V
VOH High-Level Digital Output Voltage All digital pins except SDA and SCL, IOVDD = 1.8-V operation For IOL = 2 mA and IOH = –2 mA IOVDD – 0.45 V
VOL Low-Level Digital Output Vvoltage 0.45 V
VOH High-Level Digital Output Voltage All digital pins except SDA and SCL, IOVDD = 3.3-V operation For IOL = 2 mA and IOH = –2 mA 2.4 V
VOL Low-Level Digital Output Voltage 0.4 V
IIH High-Level Digital Input Leakage Current Input = IOVDD –5 0.1 5 µA
IIL Low-Level Digital Input Leakage Current Input = Ground –5 0.1 5 µA
MISCELLANEOUS
TTRIP Thermal Trip Point 140 °C

I2C Timing Requirements

For I2C interface signals over recommended operating conditions (unless otherwise noted). See Figure 1(1)
SYMBOL PARAMETER CONDITIONS Standard-Mode Fast-Mode UNIT
MIN MAX MIN MAX
fSCL SCL Clock Frequency 0 100 0 400 kHz
tHD;STA Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. 4 0.6 μs
tLOW LOW Period of the SCL Clock 4.7 1.3 μs
tHIGH HIGH Period of the SCL Clock 4 0.6 μs
tSU;STA Setup Time for a Repeated START Condition 4.7 0.6 μs
tHD;DAT Data Hold Time: For I2C Bus Devices 0 3.45 0 0.9 μs
tSU;DAT Data Setup Time 250 100 ns
tr SDA and SCL Rise Time 1000 20 + 0.1 × Cb 300 ns
tf SDA and SCL Fall Time 300 20 + 0.1 × Cb 300 ns
tSU;STO Setup Time for STOP Condition 4 0.6 μs
tBUF Bus Free Time Between a STOP and START Condition 4.7 1.3 μs
Cb Capacitive Load for Each Bus Line 400 400 pF
All timing specifications are measured at characterization but not tested at final test.

SPI Timing Requirements

For SPI interface signals over recommended operating conditions (unless otherwise noted). See Figure 2(1)
SYMBOL PARAMETER CONDITIONS IOVDD = 1.8 V IOVDD = 3.3 V UNIT
MIN MAX MIN MAX
tsck SCLK Period 40 30 ns
tsckh SCLK Pulse Width High 40 30 ns
tsckl SCLK Pulse Width Low 40 30 ns
tlead Enable Lead Time 40 30 ns
ttrail Enable Trail Time 40 30 ns
td;seqxfr Sequential Transfer Delay 40 30 ns
ta Slave DOUT Access Time 35 25 ns
tdis Slave DOUT Disable Time 35 25 ns
tsu DIN Data Setup Time 8 8 ns
th;DIN DIN Data Hold Time 8 8 ns
tv;DOUT DOUT Data Valid Time 35 25 ns
tr SCLK Rise Time 4 4 ns
tf SCLK Fall Time 4 4 ns
All timing specifications are measured at characterization but not tested at final test.

I2S/LJF/RJF Timing in Master Mode

All specifications at TA = –40°C to 85°C, IOVDD data sheet limits, VIL and VIH applied, VOL and VOH measured at datasheet limits, lumped capacitive load of 20 pF on output pins unless otherwise noted. See Figure 3(1)
SYMBOL PARAMETER CONDITIONS IOVDD = 1.8 V IOVDD = 3.3 V UNIT
MIN MAX MIN MAX
td(WS) BCLK to WCLK delay 50% of BCLK to 50% of WCLK 35 25 ns
td(DO-WS) WCLK to DOUT Delay (For LJF Mode Only) 50% of WCLK to 50% of DOUT 35 25 ns
td(DO-BCLK) BCLK to DOUT Delay 50% of BCLK to 50% of DOUT 35 25 ns
ts(DI) DIN Setup 8 8 ns
th(DI) DIN Hold 8 8 ns
tr Rise Time 10%-90% Rise Time 8 4 ns
tf Fall Time 90%-10% Fall Time 8 4 ns
All timing specifications are measured at characterization but not tested at final test.

I2S/LJF/RJF Timing in Slave Mode

All specifications at TA = –40°C to 85°C, IOVDD data sheet limits, VIL and VIH applied, VOL and VOH measured at datasheet limits, lumped capacitive load of 20 pF on output pins unless otherwise noted. See Figure 4(1)
SYMBOL PARAMETER CONDITIONS IOVDD = 1.8 V IOVDD = 3.3 V UNIT
MIN MAX MIN MAX
tH(BCLK) BCLK High Period 40 30 ns
tL(BCLK) BCLK Low Period 40 30 ns
ts(WS) (WS) 8 8 ns
th(WS) WCLK Hold 8 8 ns
td(DO-WS) WCLK to DOUT Delay (For LJF Mode Only) 50% of WCLK to 50% of DOUT 35 25 ns
td(DO-BCLK) BCLK to DOUT Delay 50% of BCLK to 50% of DOUT 35 25 ns
ts(DI) DIN Setup 8 8 ns
th(DI) DIN Hold 8 8 ns
tr Rise Time 10%-90% Rise Time 8 4 ns
tf Fall Time 90%-10% Fall Time 8 4 ns

DSP Timing in Master Mode

All specifications at TA = –40°C to 85°C, IOVDD data sheet limits, VIL and VIH applied, VOL and VOH measured at datasheet limits, lumped capacitive load of 20 pF on output pins unless otherwise noted. See Figure 5(1)
SYMBOL PARAMETER CONDITIONS IOVDD = 1.8 V IOVDD = 3.3 V UNIT
MIN MAX MIN MAX
td(WS) BCLK to WCLK delay 50% of BCLK to 50% of WCLK 35 25 ns
td(DO-BCLK) BCLK to DOUT delay 50% of BLCK to 50% of DOUT 35 25 ns
ts(DI) DIN Setup 8 8 ns
th(DI) DIN Hold 8 8 ns
tr Rise Time 10%-90% Rise Time 8 4 ns
tf Fall Time 90%-10% Fall Time 8 4 ns

DSP Timing in Slave Mode

All specifications at 25°C, IOVDD = 1.8 V Ssee Figure 6(1)
SYMBOL PARAMETER CONDITIONS IOVDD=1.8V IOVDD=3.3V UNIT
MIN MAX MIN MAX
tH(BCLK) BCLK High Period 40 30 ns
tL(BCLK) BCLK Low Period 40 30 ns
ts(WS) WCLK setup 8 8 ns
th(WS) WCLK Hold 8 8 ns
td(DO-BCLK) BCLK to DOUT Delay (For LJF Mode Only) 50% BCLK to 50% DOUT 35 25 ns
ts(DI) DIN Setup 8 8 ns
th(DI) DIN Hold 8 8 ns
tr Rise Time 10%-90% Rise Time 8 4 ns
tf Fall Time 90%-10% Fall Time 8 4 ns
TAS2557 i2c_timing.gif Figure 1. I2C Timing
TAS2557 if_tim_los585.gif Figure 2. SPI Interface Timing Diagram
TAS2557 master_tim_los585.gif Figure 3. I2S/LJF/RJF Timing in Master Mode
TAS2557 i2sljfrlf_los585.gif Figure 4. I2S/LJF/RJF Timing in Slave Mode
TAS2557 dsp_tim_los585.gif Figure 5. DSP Timing in Master Mode
TAS2557 dsp_slave_los585.gif Figure 6. DSP Timing in Slave Mode

Typical Characteristics

VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, RESET = IOVDD, RL = 8 Ω + 33 µH, I2S Digital Input, ROM Mode 1 (Unless Otherwise Noted).
TAS2557 D001_SLASEC2_TAS2557.gif
8 Ω + 33 µH Freq = 1 kHz
Figure 7. THD+N vs Output Power
TAS2557 D003_SLASEC2_TAS2557.gif
8 Ω + 33 µH POUT = 1 W
Figure 9. THD+N vs Frequency
TAS2557 D005_SLASEC2_TAS2557.gif
Figure 11. VBAT Supply Ripple Rejection vs Frequency
TAS2557 D007_SLASEC2_TAS2557.gif
8 Ω + 33 µH
Figure 13. Efficiency vs Output Power
TAS2557 D009_SLASEC2_TAS2557.gif
4 Ω + 16 µH
Figure 15. Output Power for 1% THD+N vs VBAT
TAS2557 D002_SLASEC2_TAS2557.gif
4 Ω + 16 µH Freq = 1 kHz
Figure 8. THD+N vs Output Power
TAS2557 D004_SLASEC2_TAS2557.gif
4 Ω + 16 µH POUT = 1 W
Figure 10. THD+N vs Frequency
TAS2557 D006_SLASEC2_TAS2557.gif
Figure 12. AVDD Supply Ripple Rejection vs Frequency
TAS2557 D008_SLASEC2_TAS2557.gif
4 Ω + 16 µH
Figure 14. Efficiency vs Output Power
TAS2557 D010_SLASEC2_TAS2557.gif
4 Ω + 16 µH
Figure 16. Quiescent Current vs VBAT