ZHCSFP7A November   2016  – February 2017 TAS2557

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. 说明(续)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  I2C Timing Requirements
    7. 8.7  SPI Timing Requirements
    8. 8.8  I2S/LJF/RJF Timing in Master Mode
    9. 8.9  I2S/LJF/RJF Timing in Slave Mode
    10. 8.10 DSP Timing in Master Mode
    11. 8.11 DSP Timing in Slave Mode
    12. 8.12 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  General I2C Operation
      2. 10.3.2  Single-Byte and Multiple-Byte Transfers
      3. 10.3.3  Single-Byte Write
      4. 10.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 10.3.5  Single-Byte Read
      6. 10.3.6  Multiple-Byte Read
      7. 10.3.7  General SPI Operation
      8. 10.3.8  Class-D Edge Rate Control
      9. 10.3.9  IV Sense
      10. 10.3.10 Battery Tracking AGC
      11. 10.3.11 Boost Control
        1. 10.3.11.1 Boost Mode
        2. 10.3.11.2 Configurable Boost Current Limit (ILIM)
      12. 10.3.12 Thermal Fold-back
      13. 10.3.13 Fault Protection
        1. 10.3.13.1 Speaker Over-Current
        2. 10.3.13.2 Analog Under-Voltage
        3. 10.3.13.3 Die Over-Temperature
        4. 10.3.13.4 Clocking Faults
      14. 10.3.14 Brownout
      15. 10.3.15 Spread Spectrum vs Synchronized
      16. 10.3.16 IRQs and Flags
      17. 10.3.17 Software Reset
      18. 10.3.18 PurePath Console 3 Software TAS2557 Application
    4. 10.4 Device Functional Modes
      1. 10.4.1 Audio Digital I/O Interface
        1. 10.4.1.1 I2S Mode
        2. 10.4.1.2 DSP Mode
        3. 10.4.1.3 Right-Justified Mode (RJF)
        4. 10.4.1.4 Left-Justified Mode (LJF)
      2. 10.4.2 Mono PCM Mode
      3. 10.4.3 Stereo Application Example - TDM Mode
    5. 10.5 Operational Modes
      1. 10.5.1 Hardware Shutdown
      2. 10.5.2 Software Shutdown
      3. 10.5.3 Low Power Sleep
      4. 10.5.4 Software Reset
      5. 10.5.5 Device Processing Modes
        1. 10.5.5.1 Mode 1 - PCM input playback only
        2. 10.5.5.2 Mode 2 - PCM input playback + PCM IVsense output
        3. 10.5.5.3 Mode 3 - Smart Amp Mode
    6. 10.6 Programming
      1. 10.6.1 Code Loading and CRC check
      2. 10.6.2 Device Power Up and Unmute Sequence
      3. 10.6.3 Device Mute and Power Down Sequence
  11. 11Applications and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Detailed Design Procedure
          1. 11.2.1.1.1 Mono/Stereo Configuration
          2. 11.2.1.1.2 Boost Converter Passive Devices
          3. 11.2.1.1.3 EMI Passive Devices
          4. 11.2.1.1.4 Miscellaneous Passive Devices
      2. 11.2.2 Application Performance Plots
    3. 11.3 Initialization Set Up
  12. 12Power Supply Recommendations
    1. 12.1 Power Supplies
    2. 12.2 Power Supply Sequencing
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Register Map
    1. 14.1 Register Map Summary
      1. 14.1.1 Register Summary Table Book=0x00 Page=0x00
      2. 14.1.2 Register Summary Table Book=0x00 Page=0x01
      3. 14.1.3 Register Summary Table Book=0x00 Page=0x02
    2. 14.2 Register Maps
      1. 14.2.1   PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
      2. 14.2.2   RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
      3. 14.2.3   POWER_1 (book=0x00 page=0x00 address=0x04) [reset=0h]
      4. 14.2.4   POWER_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
      5. 14.2.5   SPK_GAIN_EDGE (book=0x00 page=0x00 address=0x06) [reset=0h]
      6. 14.2.6   MUTE (book=0x00 page=0x00 address=0x07) [reset=0h]
      7. 14.2.7   SNS_CTRL (book=0x00 page=0x00 address=0x08) [reset=0h]
      8. 14.2.8   BOOST_CTRL_1 (book=0x00 page=0x00 address=0x09) [reset=0h]
      9. 14.2.9   SAR_CTRL_2 (book=0x00 page=0x00 address=0x14) [reset=32h]
      10. 14.2.10  SAR_CTRL_3 (book=0x00 page=0x00 address=0x15) [reset=4h]
      11. 14.2.11  SAR_VBAT_MSB (book=0x00 page=0x00 address=0x16) [reset=0h]
      12. 14.2.12  SAR_VBAT_LSB (book=0x00 page=0x00 address=0x17) [reset=0h]
      13. 14.2.13  SAR_VBST_MSB (book=0x00 page=0x00 address=0x18) [reset=0h]
      14. 14.2.14  SAR_VBST_LSB (book=0x00 page=0x00 address=0x19) [reset=0h]
      15. 14.2.15  SAR_TMP1_MSB (book=0x00 page=0x00 address=0x1A) [reset=0h]
      16. 14.2.16  SAR_TMP1_LSB (book=0x00 page=0x00 address=0x1B) [reset=0h]
      17. 14.2.17  SAR_TMP2_MSB (book=0x00 page=0x00 address=0x1C) [reset=0h]
      18. 14.2.18  SAR_TMP2_LSB (book=0x00 page=0x00 address=0x1D) [reset=0h]
      19. 14.2.19  CRC_CHECKSUM (book=0x00 page=0x00 address=0x20) [reset=0h]
      20. 14.2.20  CRC_RESET (book=0x00 page=0x00 address=0x21) [reset=0h]
      21. 14.2.21  DSP_CTRL (book=0x00 page=0x00 address=0x22) [reset=1h]
      22. 14.2.22  SSM_CTRL (book=0x00 page=0x00 address=0x28) [reset=0h]
      23. 14.2.23  ASI_CTRL_1 (book=0x00 page=0x00 address=0x2A) [reset=0h]
      24. 14.2.24  BOOST_CTRL_2 (book=0x00 page=0x00 address=0x2B) [reset=3h]
      25. 14.2.25  CLOCK_CTRL_1 (book=0x00 page=0x00 address=0x2C) [reset=0h]
      26. 14.2.26  CLOCK_CTRL_2 (book=0x00 page=0x00 address=0x2D) [reset=17h]
      27. 14.2.27  CLOCK_CTRL_3 (book=0x00 page=0x00 address=0x2E) [reset=0h]
      28. 14.2.28  ASI_CTRL_2 (book=0x00 page=0x00 address=0x2F) [reset=0h]
      29. 14.2.29  CLOCK_CTRL_4 (book=0x00 page=0x00 address=0x32) [reset=0h]
      30. 14.2.30  DEBUG_1 (book=0x00 page=0x00 address=0x35) [reset=0h]
      31. 14.2.31  POWER_STATUS (book=0x00 page=0x00 address=0x64) [reset=0h]
      32. 14.2.32  DSP_BOOT_STATUS (book=0x00 page=0x00 address=0x65) [reset=0h]
      33. 14.2.33  INT_DET_1 (book=0x00 page=0x00 address=0x68) [reset=0h]
      34. 14.2.34  INT_DET_2 (book=0x00 page=0x00 address=0x6C) [reset=0h]
      35. 14.2.35  LOW_POWER (book=0x00 page=0x00 address=0x79) [reset=0h]
      36. 14.2.36  BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
      37. 14.2.37  PAGE (book=0x00 page=0x01 address=0x00) [reset=1h]
      38. 14.2.38  ASI1_FORMAT (book=0x00 page=0x01 address=0x01) [reset=10h]
      39. 14.2.39  ASI1_OFFSET_1 (book=0x00 page=0x01 address=0x03) [reset=0h]
      40. 14.2.40  ASI1_BUSKEEP (book=0x00 page=0x01 address=0x05) [reset=0h]
      41. 14.2.41  ASI1_BCLK (book=0x00 page=0x01 address=0x08) [reset=0h]
      42. 14.2.42  ASI1_WCLK (book=0x00 page=0x01 address=0x09) [reset=8h]
      43. 14.2.43  ASI1_DIN_DOUT (book=0x00 page=0x01 address=0x0C) [reset=0h]
      44. 14.2.44  ASI1_BDIV_CLK (book=0x00 page=0x01 address=0x0D) [reset=1h]
      45. 14.2.45  ASI1_BDIV_RATIO (book=0x00 page=0x01 address=0x0E) [reset=2h]
      46. 14.2.46  ASI1_WDIV_RATIO (book=0x00 page=0x01 address=0x0F) [reset=20h]
      47. 14.2.47  ASI1_CLK_OUT (book=0x00 page=0x01 address=0x10) [reset=0h]
      48. 14.2.48  ASI2_FORMAT (book=0x00 page=0x01 address=0x15) [reset=10h]
      49. 14.2.49  ASI2_OFFSET_1 (book=0x00 page=0x01 address=0x17) [reset=0h]
      50. 14.2.50  ASI2_BUSKEEP (book=0x00 page=0x01 address=0x19) [reset=0h]
      51. 14.2.51  ASI2_BCLK (book=0x00 page=0x01 address=0x1C) [reset=20h]
      52. 14.2.52  ASI2_WCLK (book=0x00 page=0x01 address=0x1D) [reset=28h]
      53. 14.2.53  ASI2_DIN_DOUT (book=0x00 page=0x01 address=0x20) [reset=38h]
      54. 14.2.54  ASI2_BDIV_CLK (book=0x00 page=0x01 address=0x21) [reset=1h]
      55. 14.2.55  ASI2_BDIV_RATIO (book=0x00 page=0x01 address=0x22) [reset=2h]
      56. 14.2.56  ASI2_WDIV_RATIO (book=0x00 page=0x01 address=0x23) [reset=20h]
      57. 14.2.57  ASI2_CLK_OUT (book=0x00 page=0x01 address=0x24) [reset=33h]
      58. 14.2.58  GPIO1_PIN (book=0x00 page=0x01 address=0x3D) [reset=1h]
      59. 14.2.59  GPIO2_PIN (book=0x00 page=0x01 address=0x3E) [reset=1h]
      60. 14.2.60  GPIO3_PIN (book=0x00 page=0x01 address=0x3F) [reset=10h]
      61. 14.2.61  GPIO4_PIN (book=0x00 page=0x01 address=0x40) [reset=7h]
      62. 14.2.62  GPIO5_PIN (book=0x00 page=0x01 address=0x41) [reset=0h]
      63. 14.2.63  GPIO6_PIN (book=0x00 page=0x01 address=0x42) [reset=0h]
      64. 14.2.64  GPIO7_PIN (book=0x00 page=0x01 address=0x43) [reset=0h]
      65. 14.2.65  GPIO8_PIN (book=0x00 page=0x01 address=0x44) [reset=0h]
      66. 14.2.66  GPIO9_PIN (book=0x00 page=0x01 address=0x45) [reset=0h]
      67. 14.2.67  GPIO10_PIN (book=0x00 page=0x01 address=0x46) [reset=0h]
      68. 14.2.68  GPI_PIN (book=0x00 page=0x01 address=0x4D) [reset=0h]
      69. 14.2.69  GPIO_HIZ_1 (book=0x00 page=0x01 address=0x4F) [reset=0h]
      70. 14.2.70  GPIO_HIZ_2 (book=0x00 page=0x01 address=0x50) [reset=0h]
      71. 14.2.71  GPIO_HIZ_3 (book=0x00 page=0x01 address=0x51) [reset=0h]
      72. 14.2.72  GPIO_HIZ_4 (book=0x00 page=0x01 address=0x52) [reset=0h]
      73. 14.2.73  GPIO_HIZ_5 (book=0x00 page=0x01 address=0x53) [reset=0h]
      74. 14.2.74  BIT_BANG_OUT1 (book=0x00 page=0x01 address=0x58) [reset=0h]
      75. 14.2.75  BIT_BANG_OUT2 (book=0x00 page=0x01 address=0x59) [reset=0h]
      76. 14.2.76  BIT_BANG_IN1 (book=0x00 page=0x01 address=0x5A) [reset=0h]
      77. 14.2.77  BIT_BANG_IN2 (book=0x00 page=0x01 address=0x5B) [reset=0h]
      78. 14.2.78  BIT_BANG_IN3 (book=0x00 page=0x01 address=0x5C) [reset=0h]
      79. 14.2.79  ASIM_BUSKEEP (book=0x00 page=0x01 address=0x60) [reset=0h]
      80. 14.2.80  ASIM_MODE (book=0x00 page=0x01 address=0x61) [reset=8h]
      81. 14.2.81  ASIM_NUM_DEV (book=0x00 page=0x01 address=0x62) [reset=0h]
      82. 14.2.82  ASIM_FORMAT (book=0x00 page=0x01 address=0x63) [reset=10h]
      83. 14.2.83  ASIM_BDIV_CLK (book=0x00 page=0x01 address=0x64) [reset=1h]
      84. 14.2.84  ASIM_BDIV_RATIO (book=0x00 page=0x01 address=0x65) [reset=2h]
      85. 14.2.85  ASIM_WDIV_RATIO_1 (book=0x00 page=0x01 address=0x66) [reset=0h]
      86. 14.2.86  ASIM_WDIV_RATIO_2 (book=0x00 page=0x01 address=0x67) [reset=20h]
      87. 14.2.87  ASIM_BCLK (book=0x00 page=0x01 address=0x68) [reset=40h]
      88. 14.2.88  ASIM_WCLK (book=0x00 page=0x01 address=0x69) [reset=38h]
      89. 14.2.89  ASIM_DIN (book=0x00 page=0x01 address=0x6A) [reset=70h]
      90. 14.2.90  INT_GEN_1 (book=0x00 page=0x01 address=0x6C) [reset=0h]
      91. 14.2.91  INT_GEN_2 (book=0x00 page=0x01 address=0x6D) [reset=0h]
      92. 14.2.92  INT_GEN_3 (book=0x00 page=0x01 address=0x6E) [reset=0h]
      93. 14.2.93  INT_GEN_4 (book=0x00 page=0x01 address=0x6F) [reset=0h]
      94. 14.2.94  INT_GEN_5 (book=0x00 page=0x01 address=0x70) [reset=0h]
      95. 14.2.95  INT_GEN_6 (book=0x00 page=0x01 address=0x71) [reset=0h]
      96. 14.2.96  INT_IND_MODE (book=0x00 page=0x01 address=0x72) [reset=0h]
      97. 14.2.97  MAIN_CLK_PIN (book=0x00 page=0x01 address=0x73) [reset=Dh]
      98. 14.2.98  PLL_CLK_PIN (book=0x00 page=0x01 address=0x74) [reset=Dh]
      99. 14.2.99  CLKOUT_MUX (book=0x00 page=0x01 address=0x75) [reset=Dh]
      100. 14.2.100 CLKOUT_CDIV_RATIO (book=0x00 page=0x01 address=0x76) [reset=1h]
      101. 14.2.101 I2C_MISC (book=0x00 page=0x01 address=0x7C) [reset=0h]
      102. 14.2.102 DEVICE_ID (book=0x00 page=0x01 address=0x7D) [reset=12h]
      103. 14.2.103 PAGE (book=0x00 page=0x02 address=0x00) [reset=1h]
      104. 14.2.104 RAMP_CTRL (book=0x00 page=0x02 address=0x06) [reset=0h]
      105. 14.2.105 PROTECTION_CFG (book=0x00 page=0x02 address=0x09) [reset=3h]
  15. 15器件和文档支持
    1. 15.1 文档支持
    2. 15.2 社区资源
    3. 15.3 商标
    4. 15.4 静电放电警告
    5. 15.5 Glossary
  16. 16机械、封装和可订购信息
    1. 16.1 封装尺寸

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YZ|42
订购信息

Register Map

See the General I2C Operation section for more details on addressing. Register settings should be set based on the files generated from the PPC3 GUI. Because the TAS2557 is a complex system including the internal software, changes made in the TAS2557 registers not known in the PPC3 generated configurations can result in the speaker protection not operating correctly. Changes should be made from within PurePath Console 3 Software TAS2557 Application instead of manually changing registers when possible. Configuration files with needed options can be generated from PPC3 to prevent invalid configurations.

Register Map Summary

Register Summary Table Book=0x00 Page=0x00

AddrRegisterDescriptionSection
0x00PAGEPage Select PAGE (book=0x00 page=0x01 address=0x00) [reset=1h]
0x01RESETSoftware Reset RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
0x04POWER_1Power Up 1 POWER_1 (book=0x00 page=0x00 address=0x04) [reset=0h]
0x05POWER_2Power Up 2 POWER_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
0x06SPK_GAIN_EDGEClass-D Speaker Configuration SPK_GAIN_EDGE (book=0x00 page=0x00 address=0x06) [reset=0h]
0x07MUTEMute Configuration MUTE (book=0x00 page=0x00 address=0x07) [reset=0h]
0x08SNS_CTRLSense Channel Control SNS_CTRL (book=0x00 page=0x00 address=0x08) [reset=0h]
0x09BOOST_CTRL_1Boost Control 1 BOOST_CTRL_1 (book=0x00 page=0x00 address=0x09) [reset=0h]
0x14SAR_CTRL_2SAR Control 2 SAR_CTRL_2 (book=0x00 page=0x00 address=0x14) [reset=32h]
0x15SAR_CTRL_3SAR Control 3 SAR_CTRL_3 (book=0x00 page=0x00 address=0x15) [reset=4h]
0x16SAR_VBAT_MSBSAR VBAT Readback SAR_VBAT_MSB (book=0x00 page=0x00 address=0x16) [reset=0h]
0x17SAR_VBAT_LSBSAR VBAT Readback SAR_VBAT_LSB (book=0x00 page=0x00 address=0x17) [reset=0h]
0x18SAR_VBST_MSBSAR VBOOST Readback SAR_VBST_MSB (book=0x00 page=0x00 address=0x18) [reset=0h]
0x19SAR_VBST_LSBSAR VBOOST Readback SAR_VBST_LSB (book=0x00 page=0x00 address=0x19) [reset=0h]
0x1ASAR_TMP1_MSBSAR TEMP1 Readback SAR_TMP1_MSB (book=0x00 page=0x00 address=0x1A) [reset=0h]
0x1BSAR_TMP1_LSBSAR TEMP1 Readback SAR_TMP1_LSB (book=0x00 page=0x00 address=0x1B) [reset=0h]
0x1CSAR_TMP2_MSBSAR TEMP2 Readback SAR_TMP2_MSB (book=0x00 page=0x00 address=0x1C) [reset=0h]
0x1DSAR_TMP2_LSBSAR TEMP2 Readback SAR_TMP2_LSB (book=0x00 page=0x00 address=0x1D) [reset=0h]
0x20CRC_CHECKSUMChecksum CRC_CHECKSUM (book=0x00 page=0x00 address=0x20) [reset=0h]
0x21CRC_RESETChecksum Reset CRC_RESET (book=0x00 page=0x00 address=0x21) [reset=0h]
0x22DSP_CTRLDSP Control DSP_CTRL (book=0x00 page=0x00 address=0x22) [reset=1h]
0x28SSM_CTRLSpread-Spectrum Control SSM_CTRL (book=0x00 page=0x00 address=0x28) [reset=0h]
0x2AASI_CTRL_1ASI Control 1 ASI_CTRL_1 (book=0x00 page=0x00 address=0x2A) [reset=0h]
0x2BBOOST_CTRL_2Boost Control 1 BOOST_CTRL_2 (book=0x00 page=0x00 address=0x2B) [reset=3h]
0x2CCLOCK_CTRL_1Clock Control 1 CLOCK_CTRL_1 (book=0x00 page=0x00 address=0x2C) [reset=0h]
0x2DCLOCK_CTRL_2Clock Control 2 CLOCK_CTRL_2 (book=0x00 page=0x00 address=0x2D) [reset=17h]
0x2ECLOCK_CTRL_3Clock Control 3 CLOCK_CTRL_3 (book=0x00 page=0x00 address=0x2E) [reset=0h]
0x2FASI_CTRL_2ASI Control 2 ASI_CTRL_2 (book=0x00 page=0x00 address=0x2F) [reset=0h]
0x32CLOCK_CTRL_4Clock Control 4 CLOCK_CTRL_4 (book=0x00 page=0x00 address=0x32) [reset=0h]
0x35DEBUG_1Debug Register 1 DEBUG_1 (book=0x00 page=0x00 address=0x35) [reset=0h]
0x64POWER_STATUSPower Up Status POWER_STATUS (book=0x00 page=0x00 address=0x64) [reset=0h]
0x65DSP_BOOT_STATUSDSP Boost Status DSP_BOOT_STATUS (book=0x00 page=0x00 address=0x65) [reset=0h]
0x68INT_DET_1Interrupt Detected 1 INT_DET_1 (book=0x00 page=0x00 address=0x68) [reset=0h]
0x6CINT_DET_2Interrupt Detected 2 INT_DET_2 (book=0x00 page=0x00 address=0x6C) [reset=0h]
0x79LOW_POWERLower Power Shutdown LOW_POWER (book=0x00 page=0x00 address=0x79) [reset=0h]
0x7FBOOKBook Selection BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]

Register Summary Table Book=0x00 Page=0x01

AddrRegisterDescriptionSection
0x00PAGEPage Select PAGE (book=0x00 page=0x01 address=0x00) [reset=1h]
0x01ASI1_FORMATASI1 Format ASI1_FORMAT (book=0x00 page=0x01 address=0x01) [reset=10h]
0x03ASI1_OFFSET_1ASI1 Offset ASI1_OFFSET_1 (book=0x00 page=0x01 address=0x03) [reset=0h]
0x04ASI1_OFFSET_2ASI1 Offset Second Slot
0x05ASI1_BUSKEEPASI1 Buskeeper ASI1_BUSKEEP (book=0x00 page=0x01 address=0x05) [reset=0h]
0x08ASI1_BCLKASI1 BCLK ASI1_BCLK (book=0x00 page=0x01 address=0x08) [reset=0h]
0x09ASI1_WCLKASI1 WCLK ASI1_WCLK (book=0x00 page=0x01 address=0x09) [reset=8h]
0x0CASI1_DIN_DOUTASI1 DIN/DOUT ASI1_DIN_DOUT (book=0x00 page=0x01 address=0x0C) [reset=0h]
0x0DASI1_BDIV_CLKASI1 BDIV Clock ASI1_BDIV_CLK (book=0x00 page=0x01 address=0x0D) [reset=1h]
0x0EASI1_BDIV_RATIOASI1 BDIV Ratio ASI1_BDIV_RATIO (book=0x00 page=0x01 address=0x0E) [reset=2h]
0x0FASI1_WDIV_RATIOASI1 WDIV Ratio ASI1_WDIV_RATIO (book=0x00 page=0x01 address=0x0F) [reset=20h]
0x10ASI1_CLK_OUTASI1 Clock Source ASI1_CLK_OUT (book=0x00 page=0x01 address=0x10) [reset=0h]
0x15ASI2_FORMATASI2 Format ASI2_FORMAT (book=0x00 page=0x01 address=0x15) [reset=10h]
0x17ASI2_OFFSET_1ASI2 Offset ASI2_OFFSET_1 (book=0x00 page=0x01 address=0x17) [reset=0h]
0x18ASI2_OFFSET_2ASI2 Offset Second Slot
0x19ASI2_BUSKEEPASI2 Buskeeper ASI2_BUSKEEP (book=0x00 page=0x01 address=0x19) [reset=0h]
0x1CASI2_BCLKASI2 BCLK ASI2_BCLK (book=0x00 page=0x01 address=0x1C) [reset=20h]
0x1DASI2_WCLKASI2 WCLK ASI2_WCLK (book=0x00 page=0x01 address=0x1D) [reset=28h]
0x20ASI2_DIN_DOUTASI2 DIN/DOUT ASI2_DIN_DOUT (book=0x00 page=0x01 address=0x20) [reset=38h]
0x21ASI2_BDIV_CLKASI2 BDIV Clock ASI2_BDIV_CLK (book=0x00 page=0x01 address=0x21) [reset=1h]
0x22ASI2_BDIV_RATIOASI2 BDIV Ratio ASI2_BDIV_RATIO (book=0x00 page=0x01 address=0x22) [reset=2h]
0x23ASI2_WDIV_RATIOASI2 WDIV Ratio ASI2_WDIV_RATIO (book=0x00 page=0x01 address=0x23) [reset=20h]
0x24ASI2_CLK_OUTASI2 Clock Source ASI2_CLK_OUT (book=0x00 page=0x01 address=0x24) [reset=33h]
0x3DGPIO1_PINGPIO1 GPIO1_PIN (book=0x00 page=0x01 address=0x3D) [reset=1h]
0x3EGPIO2_PINGPIO2 GPIO2_PIN (book=0x00 page=0x01 address=0x3E) [reset=1h]
0x3FGPIO3_PINGPIO3 GPIO3_PIN (book=0x00 page=0x01 address=0x3F) [reset=10h]
0x40GPIO4_PINGPIO4 GPIO4_PIN (book=0x00 page=0x01 address=0x40) [reset=7h]
0x41GPIO5_PINGPIO5 GPIO5_PIN (book=0x00 page=0x01 address=0x41) [reset=0h]
0x42GPIO6_PINGPIO6 GPIO6_PIN (book=0x00 page=0x01 address=0x42) [reset=0h]
0x43GPIO7_PINGPIO7 GPIO7_PIN (book=0x00 page=0x01 address=0x43) [reset=0h]
0x44GPIO8_PINGPIO8 GPIO8_PIN (book=0x00 page=0x01 address=0x44) [reset=0h]
0x45GPIO9_PINGPIO9 GPIO9_PIN (book=0x00 page=0x01 address=0x45) [reset=0h]
0x46GPIO10_PINGPIO10 GPIO10_PIN (book=0x00 page=0x01 address=0x46) [reset=0h]
0x4DGPI_PINGPI Pin Mode GPI_PIN (book=0x00 page=0x01 address=0x4D) [reset=0h]
0x4FGPIO_HIZ_1GPIO HiZ 1 GPIO_HIZ_1 (book=0x00 page=0x01 address=0x4F) [reset=0h]
0x50GPIO_HIZ_2GPIO HiZ 2 GPIO_HIZ_2 (book=0x00 page=0x01 address=0x50) [reset=0h]
0x51GPIO_HIZ_3GPIO HiZ 3 GPIO_HIZ_3 (book=0x00 page=0x01 address=0x51) [reset=0h]
0x52GPIO_HIZ_4GPIO HiZ 4 GPIO_HIZ_4 (book=0x00 page=0x01 address=0x52) [reset=0h]
0x53GPIO_HIZ_5GPIO HiZ 5 GPIO_HIZ_5 (book=0x00 page=0x01 address=0x53) [reset=0h]
0x58BIT_BANG_OUT1Bit Bang Output 1 BIT_BANG_OUT1 (book=0x00 page=0x01 address=0x58) [reset=0h]
0x59BIT_BANG_OUT2Bit Bang Output 2 BIT_BANG_OUT2 (book=0x00 page=0x01 address=0x59) [reset=0h]
0x5ABIT_BANG_IN1Bit Bang Input 1 BIT_BANG_IN1 (book=0x00 page=0x01 address=0x5A) [reset=0h]
0x5BBIT_BANG_IN2Bit Bang Input 2 BIT_BANG_IN2 (book=0x00 page=0x01 address=0x5B) [reset=0h]
0x5CBIT_BANG_IN3Bit Bang Input 3 BIT_BANG_IN3 (book=0x00 page=0x01 address=0x5C) [reset=0h]
0x60ASIM_BUSKEEPASIM Buskeeper ASIM_BUSKEEP (book=0x00 page=0x01 address=0x60) [reset=0h]
0x61ASIM_MODEASIM Mode ASIM_MODE (book=0x00 page=0x01 address=0x61) [reset=8h]
0x62ASIM_NUM_DEVASIM Number Devices ASIM_NUM_DEV (book=0x00 page=0x01 address=0x62) [reset=0h]
0x63ASIM_FORMATASIM Format ASIM_FORMAT (book=0x00 page=0x01 address=0x63) [reset=10h]
0x64ASIM_BDIV_CLKASIM BDIV Clock ASIM_BDIV_CLK (book=0x00 page=0x01 address=0x64) [reset=1h]
0x65ASIM_BDIV_RATIOASIM BDIV Ratio ASIM_BDIV_RATIO (book=0x00 page=0x01 address=0x65) [reset=2h]
0x66ASIM_WDIV_RATIO_1ASIM WDIV Ratio ASIM_WDIV_RATIO_1 (book=0x00 page=0x01 address=0x66) [reset=0h]
0x67ASIM_WDIV_RATIO_2ASIM WDIV Ratio ASIM_WDIV_RATIO_2 (book=0x00 page=0x01 address=0x67) [reset=20h]
0x68ASIM_BCLKASI1 BCLK ASIM_BCLK (book=0x00 page=0x01 address=0x68) [reset=40h]
0x69ASIM_WCLKASI1 WCLK ASIM_WCLK (book=0x00 page=0x01 address=0x69) [reset=38h]
0x6AASIM_DINASI1 DIN ASIM_DIN (book=0x00 page=0x01 address=0x6A) [reset=70h]
0x6CINT_GEN_1Interrupt Generation 1 INT_GEN_1 (book=0x00 page=0x01 address=0x6C) [reset=0h]
0x6DINT_GEN_2Interrupt Generation 2 INT_GEN_2 (book=0x00 page=0x01 address=0x6D) [reset=0h]
0x6EINT_GEN_3Interrupt Generation 3 INT_GEN_3 (book=0x00 page=0x01 address=0x6E) [reset=0h]
0x6FINT_GEN_4Interrupt Generation 4 INT_GEN_4 (book=0x00 page=0x01 address=0x6F) [reset=0h]
0x70INT_GEN_5Interrupt Generation 5 INT_GEN_5 (book=0x00 page=0x01 address=0x70) [reset=0h]
0x71INT_GEN_6Interrupt Generation 6 INT_GEN_6 (book=0x00 page=0x01 address=0x71) [reset=0h]
0x72INT_IND_MODEInterrupt Indication Mode INT_IND_MODE (book=0x00 page=0x01 address=0x72) [reset=0h]
0x73MAIN_CLK_PINMain Clock Source MAIN_CLK_PIN (book=0x00 page=0x01 address=0x73) [reset=Dh]
0x74PLL_CLK_PINPLL Clock Source PLL_CLK_PIN (book=0x00 page=0x01 address=0x74) [reset=Dh]
0x75CLKOUT_MUXCDIV_CLKIN Clock Source CLKOUT_MUX (book=0x00 page=0x01 address=0x75) [reset=Dh]
0x76CLKOUT_CDIV_RATIOCLKOUT CDIV Ratio CLKOUT_CDIV_RATIO (book=0x00 page=0x01 address=0x76) [reset=1h]
0x7CI2C_MISCI2C Misc I2C_MISC (book=0x00 page=0x01 address=0x7C) [reset=0h]
0x7DDEVICE_IDDevice ID DEVICE_ID (book=0x00 page=0x01 address=0x7D) [reset=12h]

Register Summary Table Book=0x00 Page=0x02

AddrRegisterDescriptionSection
0x00PAGEPage Select PAGE (book=0x00 page=0x01 address=0x00) [reset=1h]
0x06RAMP_CTRLClass-D Ramp Control RAMP_CTRL (book=0x00 page=0x02 address=0x06) [reset=0h]
0x09PROTECTION_CFGConfigures the Devices Protection Blocks PROTECTION_CFG (book=0x00 page=0x02 address=0x09) [reset=3h]

Register Maps

PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]

Selects the page for the next read or write.

Figure 47. PAGE Register Address: 0x00
76543210
PAGE[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. Page Select Field Descriptions

BitFieldTypeResetDescription
7-0PAGE[7:0]RW0hSelects the Register Page for the next read or write command

RESET (book=0x00 page=0x00 address=0x01) [reset=0h]

Controls the software reset

Figure 48. RESET Register Address: 0x01
76543210
ReservedRESET
R-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. Software Reset Field Descriptions

BitFieldTypeResetDescription
7-1ReservedR0hReserved
0RESETRW0h 0 = Don't care
1 = Self clearing software reset

POWER_1 (book=0x00 page=0x00 address=0x04) [reset=0h]

This register controls device power up

Figure 49. POWER_1 Register Address: 0x04
76543210
PWR_DSPPWR_PLLPWR_NDIVPWR_MDACPWR_MADCReservedReservedPWR_ERR
RW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. Power Up 1 Field Descriptions

BitFieldTypeResetDescription
7PWR_DSPRW0hDSP is
0 = Powered-down

1 = Powered-up
6PWR_PLLRW0hPLL is
0 = Powered-down

1 = Powered-up
5PWR_NDIVRW0hNDIV is
0 = Powered-down

1 = Powered-up
4PWR_MDACRW0hMDAC is
0 = Powered-down

1 = Powered-up
3PWR_MADCRW0hMADC is
0 = Powered-down

1 = Powered-up
2ReservedRW0hReserved
1ReservedRW0hReserved
0PWR_ERRRW0hReports when a VBAT brownout or clock halt condition was detected. When this is detected several internal blocks are powered down. This register must be cleared first before re-power device. Reason for error is indicated in interrupt register.
0 = No error condition

1 = Error condition detected

POWER_2 (book=0x00 page=0x00 address=0x05) [reset=0h]

This register controls device power up

Figure 50. POWER_2 Register Address: 0x05
76543210
PWR_SPKReservedPWR_BOOSTReservedPWR_ISNSPWR_VSNS
RW-0hRW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. Power Up 2 Field Descriptions

BitFieldTypeResetDescription
7PWR_SPKRW0hClass-D output is
0 = Powered-down

1 = Powered-up
6ReservedRW0hReserved
5PWR_BOOSTRW0hBoost is
0 = Powered-down

1 = Powered-up
4-2ReservedRW0hReserved
1PWR_ISNSRW0hCurrent-sense ADC is
0 = Powered-down

1 = Powered-up
0PWR_VSNSRW0hVoltage-sense ADC is
0 = Powered-down

1 = Powered-up

SPK_GAIN_EDGE (book=0x00 page=0x00 address=0x06) [reset=0h]

This register controls the DAC gain and edge rate control.

Figure 51. SPK_GAIN_EDGE Register Address: 0x06
76543210
ReservedDAC_GAIN[3:0]EDGE_RATE[2:0]
RW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. Class-D Speaker Configuration Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-3DAC_GAIN[3:0]RW0hDAC gain is
0 = 0db

1 = 1db

2 = 2db

...

14 = 14db

15 = 15db
2-0EDGE_RATE[2:0]RW0hClass-D output edge rate control is
0 = 50ns

1 = 40ns

2 = 29ns

3 = 25ns

4 = 14ns

5 = 13ns

6 = 12ns

7 = 11ns

MUTE (book=0x00 page=0x00 address=0x07) [reset=0h]

This register controls muting of various system blocks.

Figure 52. MUTE Register Address: 0x07
76543210
ReservedReservedReservedReservedReservedMUTE_ISNSMUTE_VSNS
RW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. Mute Configuration Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6ReservedRW0hReserved
5ReservedRW0hReserved
4-3ReservedRW0hReserved
2ReservedRW0hReserved
1MUTE_ISNSRW0hCurrent-sense is
0 = Unmuted

1 = Muted
0MUTE_VSNSRW0hVoltage-sense is
0 = Unmuted

1 = Muted

SNS_CTRL (book=0x00 page=0x00 address=0x08) [reset=0h]

This register controls the full scale values of current and voltage sense channels.

Figure 53. SNS_CTRL Register Address: 0x08
76543210
ReservedReservedReservedISNS_SCALE[1:0]Reserved
RW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. Sense Channel Control Field Descriptions

BitFieldTypeResetDescription
7-6ReservedRW0hReserved
5-4ReservedRW0hReserved
3ReservedRW0hReserved
2-1ISNS_SCALE[1:0]RW0hSets the current and voltage sense input range for various speaker loads. Select the value closet to the nominal load.
0 = 8 ohm load, i-sense full-scale: 1.25A

1 = 6 ohm load, i-sense full-scale: 1.5A

2 = 4 ohm load, i-sense full-scale: 1.75A
0ReservedRW0hReserved

BOOST_CTRL_1 (book=0x00 page=0x00 address=0x09) [reset=0h]

This register controls the boost operation.

Figure 54. BOOST_CTRL_1 Register Address: 0x09
76543210
ReservedReservedReservedReservedBST_MODE
RW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. Boost Control 1 Field Descriptions

BitFieldTypeResetDescription
7-6ReservedRW0hReserved
5-4ReservedRW0hReserved
3-2ReservedRW0hReserved
1ReservedRW0hReserved
0BST_MODERW0hContols the boost operation mode.
0 = Class-H operation using multi-levels.

1 = Class-G operation using one level turned on and off as needed.

SAR_CTRL_2 (book=0x00 page=0x00 address=0x14) [reset=32h]

This register controls the SAR ADC repeat interval, readback register halt, mode, and power state.

Figure 55. SAR_CTRL_2 Register Address: 0x14
76543210
ReservedSAR_RPT[2:0]SAR_RBHSAR_MODE[1:0]SAR_PWR
RW-0hRW-3hRW-0hRW-1hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 33. SAR Control 2 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4SAR_RPT[2:0]RW3hThe SAR ADC repeat interval is
0 = 0 us

1 = 50 us

2 = 250 us

3 = 1 ms

4 = 5 ms

5 = 25 ms

6 = 100 ms

7 = 1 s
3SAR_RBHRW0hUpdates to SAR readback registers halt. The readback registers should be halted while read to avoid data corruptions issues from new SAR conversions.
0 = SAR updates readback registers

1 = SAR updates halted
2-1SAR_MODE[1:0]RW1hConfigures the SAR ADC mode of operation
0 = One-shot mode

1 = Repeated scan mode

2 = DSP triggered mode

3 = Reserved
0SAR_PWRRW0hSAR ADC is
0 = Powered-down

1 = Powered-up

SAR_CTRL_3 (book=0x00 page=0x00 address=0x15) [reset=4h]

This register controls the SAR ADC inputs.

Figure 56. SAR_CTRL_3 Register Address: 0x15
76543210
ReservedReservedSAR_INVBTSAR_INVBOSAR_INTMP
RW-0hRW-0hRW-1hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. SAR Control 3 Field Descriptions

BitFieldTypeResetDescription
7-4ReservedRW0hReserved
3ReservedRW0hReserved
2SAR_INVBTRW1hSAR VBAT measurement is
0 = disabled

1 = enabled
1SAR_INVBORW0hSAR VBOOST measurement is
0 = disabled

1 = enabled
0SAR_INTMPRW0hSAR temperature measurement is
0 = disabled

1 = enabled

SAR_VBAT_MSB (book=0x00 page=0x00 address=0x16) [reset=0h]

This register contains the VBAT measurement.

Figure 57. SAR_VBAT_MSB Register Address: 0x16
76543210
SR_VBAT[9:2]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. SAR VBAT Readback Field Descriptions

BitFieldTypeResetDescription
7--2SR_VBAT[9:0]R0hVBAT Measured data by SAR ADC[9:2]

SAR_VBAT_LSB (book=0x00 page=0x00 address=0x17) [reset=0h]

This register contains the VBAT measurement.

Figure 58. SAR_VBAT_LSB Register Address: 0x17
76543210
SR_VBAT[1:0]Reserved
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. SAR VBAT Readback Field Descriptions

BitFieldTypeResetDescription
7-6SR_VBAT[1:0]R0hVBAT Measured data by SAR ADC[1:0]
5-0ReservedR0hReserved

SAR_VBST_MSB (book=0x00 page=0x00 address=0x18) [reset=0h]

This register contains the VBOOST measurement.

Figure 59. SAR_VBST_MSB Register Address: 0x18
76543210
SR_VBST[9:2]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. SAR VBOOST Readback Field Descriptions

BitFieldTypeResetDescription
7--2SR_VBST[9:0]R0hVBOOST Measured data by SAR ADC[9:2]

SAR_VBST_LSB (book=0x00 page=0x00 address=0x19) [reset=0h]

This register contains the VBOOST measurement.

Figure 60. SAR_VBST_LSB Register Address: 0x19
76543210
SR_VBST[1:0]Reserved
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 38. SAR VBOOST Readback Field Descriptions

BitFieldTypeResetDescription
7-6SR_VBST[1:0]R0hVBOOST Measured data by SAR ADC[1:0]
5-0ReservedR0hReserved

SAR_TMP1_MSB (book=0x00 page=0x00 address=0x1A) [reset=0h]

This register contains the TEMP1 measurement.

Figure 61. SAR_TMP1_MSB Register Address: 0x1A
76543210
SR_TMP1[9:2]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 39. SAR TEMP1 Readback Field Descriptions

BitFieldTypeResetDescription
7--2SR_TMP1[9:0]R0hTEMP1 Measured data by SAR ADC[9:2]

SAR_TMP1_LSB (book=0x00 page=0x00 address=0x1B) [reset=0h]

This register contains the TEMP1 measurement.

Figure 62. SAR_TMP1_LSB Register Address: 0x1B
76543210
SR_TMP1[1:0]Reserved
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 40. SAR TEMP1 Readback Field Descriptions

BitFieldTypeResetDescription
7-6SR_TMP1[1:0]R0hTEMP1 Measured data by SAR ADC[1:0]
5-0ReservedR0hReserved

SAR_TMP2_MSB (book=0x00 page=0x00 address=0x1C) [reset=0h]

This register contains the TEMP2 measurement.

Figure 63. SAR_TMP2_MSB Register Address: 0x1C
76543210
SR_TMP2[9:2]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 41. SAR TEMP2 Readback Field Descriptions

BitFieldTypeResetDescription
7--2SR_TMP2[9:0]R0hTEMP2 Measured data by SAR ADC[9:2]

SAR_TMP2_LSB (book=0x00 page=0x00 address=0x1D) [reset=0h]

This register contains the TEMP2 measurement.

Figure 64. SAR_TMP2_LSB Register Address: 0x1D
76543210
SR_TMP2[1:0]Reserved
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 42. SAR TEMP2 Readback Field Descriptions

BitFieldTypeResetDescription
7-6SR_TMP2[1:0]R0hTEMP2 Measured data by SAR ADC[1:0]
5-0ReservedR0hReserved

CRC_CHECKSUM (book=0x00 page=0x00 address=0x20) [reset=0h]

Hold the running CRC8 checksum of I2C transactions

Figure 65. CRC_CHECKSUM Register Address: 0x20
76543210
CRC_VAL[7:0]
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 43. Checksum Field Descriptions

BitFieldTypeResetDescription
7-0CRC_VAL[7:0]R0hCurrent CRC value ot all I2C transactions

CRC_RESET (book=0x00 page=0x00 address=0x21) [reset=0h]

This register is used to reset the CRC checksum.

Figure 66. CRC_RESET Register Address: 0x21
76543210
ReservedCRC_RST
RW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 44. Checksum Reset Field Descriptions

BitFieldTypeResetDescription
7-1ReservedRW0hReserved
0CRC_RSTRW0hThis self clearing bit is used to reset the CRC checksum. This is recommended to be done before PRAM code download. After download the checksum value can be read to confirm download process had any errors or was successful.
0 = normal CRC operation

1 = reset CRC and clear

DSP_CTRL (book=0x00 page=0x00 address=0x22) [reset=1h]

This controls the booting mode of the DSP

Figure 67. DSP_CTRL Register Address: 0x22
76543210
ReservedReservedReservedDSP_MODE[3:0]
RW-0hRW-0hRW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 45. DSP Control Field Descriptions

BitFieldTypeResetDescription
7-6ReservedRW0hReserved
5ReservedRW0hReserved
4ReservedRW0hReserved
3-0DSP_MODE[3:0]RW1hDSP boot in mode
0 = Reserved

1 = PCM input playback only

2 = PCM input playback and IV-sense output

3 = Smart Amp

4 = Smart Amp w/ voice on ASI2

5-15 = Reserved

SSM_CTRL (book=0x00 page=0x00 address=0x28) [reset=0h]

This enables spread-spectrum mode.

Figure 68. SSM_CTRL Register Address: 0x28
76543210
ReservedSSM_EN
RW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 46. Spread-Spectrum Control Field Descriptions

BitFieldTypeResetDescription
7-1ReservedRW0hReserved
0SSM_ENRW0hEnables spread-specturm mode of the modulator. Ramp clock must be using internal clock not sync mode. This is set in B100_P0_R40
0 = disabled

1 = enabled

ASI_CTRL_1 (book=0x00 page=0x00 address=0x2A) [reset=0h]

This register configures the ASI stereo input modes and soft stepping for mute.

Figure 69. ASI_CTRL_1 Register Address: 0x2A
76543210
ReservedASI2_CH[1:0]ASI1_CH[1:0]MUTE_SS
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 47. ASI Control 1 Field Descriptions

BitFieldTypeResetDescription
7-5ReservedRW0hReserved
4-3ASI2_CH[1:0]RW0hConfigures the ASI2 input to use
0 = left channel

1 = right channel

2 = (left + right) / 2

3 = monoPCM
2-1ASI1_CH[1:0]RW0hConfigures the ASI1 input to use
0 = left channel

1 = right channel

2 = (left + right) / 2

3 = monoPCM
0MUTE_SSRW0hWhen muting and un-muting the channel the audio playback is soft stepped.
0 = enable

1 = disable

BOOST_CTRL_2 (book=0x00 page=0x00 address=0x2B) [reset=3h]

This register controls the boost operation.

Figure 70. BOOST_CTRL_2 Register Address: 0x2B
76543210
ReservedReservedReservedBST_ILIM[1:0]
RW-0hRW-0hRW-0hRW-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 48. Boost Control 1 Field Descriptions

BitFieldTypeResetDescription
7-4ReservedRW0hReserved
3ReservedRW0hReserved
2ReservedRW0hReserved
1-0BST_ILIM[1:0]RW3hBoost current limit
0 = 1.5A

1 = 2.0A

2 = 2.5A

3 = 3.0A

CLOCK_CTRL_1 (book=0x00 page=0x00 address=0x2C) [reset=0h]

Configures the clock error detection handling

Figure 71. CLOCK_CTRL_1 Register Address: 0x2C
76543210
DSP_RSTMReservedCE1_SMCE1_ICCE2_IC[1:0]CE1_ENCE2_EN
RW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 49. Clock Control 1 Field Descriptions

BitFieldTypeResetDescription
7DSP_RSTMRW0h 0 = Reserved
6ReservedRW0hReserved
5CE1_SMRW0hWhen clock error1 is detected do soft mute using
0 = hardware mute sequence

1 = DSP mute sequence
4CE1_ICRW0hClock error detection block 1 input clock is
0 = ASI1

1 = ASI2
3-2CE2_IC[1:0]RW0hClock error detection block 2 input clock is
0 = DAC modulator clock

1 = ADC modulator clock

2 = PLL clock

3 = reserved
1CE1_ENRW0hClock error detection block 1 is
0 = disabled

1 = enabled
0CE2_ENRW0hClock error detection block 2 is
0 = disabled

1 = enabled

CLOCK_CTRL_2 (book=0x00 page=0x00 address=0x2D) [reset=17h]

Configures the clock error detection timeouts

Figure 72. CLOCK_CTRL_2 Register Address: 0x2D
76543210
ReservedReservedReservedCE1_STO[2:0]
RW-0hRW-0hRW-2hRW-7h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 50. Clock Control 2 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6ReservedRW0hReserved
5-3ReservedRW2hReserved
2-0CE1_STO[2:0]RW7hClock error detection block 1 will shutdown the device and set signal PWR_ERR if a clock input does not occur for
0 = 2.73 ms

1 = 22 ms

2 = 44 ms

3 = 87ms

4 = 174 ms

5 = 350 ms

6 = 700 ms

7 = 1.4s

CLOCK_CTRL_3 (book=0x00 page=0x00 address=0x2E) [reset=0h]

Configures the clock error detection timeouts

Figure 73. CLOCK_CTRL_3 Register Address: 0x2E
76543210
CE2_DRR[1:0]ReservedCE2_STO[2:0]
RW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 51. Clock Control 3 Field Descriptions

BitFieldTypeResetDescription
7-6CE2_DRR[1:0]RW0hFor clock error detection block 2 gain ramp-down for DAC channel is
0 = 15 us per dB

1 = 30 us per dB

2 = 60 us per dB

3 = 120 us per dB
5-3ReservedRW0hReserved
2-0CE2_STO[2:0]RW0hClock error detection block 2 will shutdown the device and set signal PWR_ERR if a clock input does not occur for
0 = 2.73 ms

1 = 22 ms

2 = 44 ms

3 = 87ms

4 = 174 ms

5 = 350 ms

6 = 700 ms

7 = 1.4s

ASI_CTRL_2 (book=0x00 page=0x00 address=0x2F) [reset=0h]

This register sets the PCM sampling rate.

Figure 74. ASI_CTRL_2 Register Address: 0x2F
76543210
ReservedReservedASI_SR[1:0]
RW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 52. ASI Control 2 Field Descriptions

BitFieldTypeResetDescription
7-3ReservedRW0hReserved
2ReservedRW0hReserved
1-0ASI_SR[1:0]RW0hSets the sampling rate of the ASI input data in PCM mode to
0 = 8kHz

1 = 16kHz

2 = 48 kHz

3 = 96kHz

CLOCK_CTRL_4 (book=0x00 page=0x00 address=0x32) [reset=0h]

Configures the clock error detection recovery

Figure 75. CLOCK_CTRL_4 Register Address: 0x32
76543210
ReservedCE2_RMCE1_RM
RW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 53. Clock Control 4 Field Descriptions

BitFieldTypeResetDescription
7-2ReservedRW0hReserved
1CE2_RMRW0hDevice automatic recovery when clock error occurs on clock error block 2
0 = enabled

1 = disabled
0CE1_RMRW0hDevice automatic recovery when clock error occurs on clock error block 1
0 = enabled

1 = disabled

DEBUG_1 (book=0x00 page=0x00 address=0x35) [reset=0h]

Debug Register 1

Figure 76. DEBUG_1 Register Address: 0x35
76543210
ReservedDPU_FRCTM_I2VINTG1_EN
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 54. Debug Register 1 Field Descriptions

BitFieldTypeResetDescription
7-3ReservedRW0hReserved
2DPU_FRCRW0h 0 = don't force power down of dummy power up
1 = force power down of dummy power up (use this if dummy power up scheme is going to a hang state)
1TM_I2VRW0hcont_tm_i2v_startup_en
0INTG1_ENRW0henz_intg1_clamping

POWER_STATUS (book=0x00 page=0x00 address=0x64) [reset=0h]

This reports the blocks power state

Figure 77. POWER_STATUS Register Address: 0x64
76543210
PUS_DACPUS_SPKPUS_BSTPUS_BPTPUS_ISNSPUS_VSNSReserved
R-0hR-0hR-0hR-0hR-0hR-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 55. Power Up Status Field Descriptions

BitFieldTypeResetDescription
7PUS_DACR0hDAC is
0 = powered down

1 = powered up
6PUS_SPKR0hClass-D output is
0 = powered down

1 = powered up
5PUS_BSTR0hBoost is
0 = powered down

1 = powered up
4PUS_BPTR0hBoost pass-thru is
0 = disabled

1 = enabled
3PUS_ISNSR0hCurrent-sense ADC is
0 = powered down

1 = powered up
2PUS_VSNSR0hVoltage-sense ADC is
0 = powered down

1 = powered up
1-0ReservedRW0hReserved

DSP_BOOT_STATUS (book=0x00 page=0x00 address=0x65) [reset=0h]

Reports the status of the DSP booting.

Figure 78. DSP_BOOT_STATUS Register Address: 0x65
76543210
ReservedDSP_BSReserved
R-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 56. DSP Boost Status Field Descriptions

BitFieldTypeResetDescription
7-3ReservedR0hReserved
2DSP_BSR0hThe DSP booting is
0 = completed; Host can write coefficient memories

0 = in progress ; Host cannot write coefficient memories
1-0ReservedR0hReserved

INT_DET_1 (book=0x00 page=0x00 address=0x68) [reset=0h]

Sticky register used to indicate the source of an interrupt trigger. Register is cleared once read.

Figure 79. INT_DET_1 Register Address: 0x68
76543210
INT_OCINT_UVReservedINT_OTINT_BOINT_CLINT_SCReserved
R-0hR-0hR-0hR-0hR-0hR-0hR-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 57. Interrupt Detected 1 Field Descriptions

BitFieldTypeResetDescription
7INT_OCR0hSticky bit indicating that speaker over current condition
0 = did not occurred since last read

1 = occurred since last read
6INT_UVR0hSticky bit indicating that analog under voltage condition
0 = did not occurred since last read

1 = occurred since last read
5ReservedR0hReserved
4INT_OTR0hSticky bit indicating that die over-temperature condition
0 = did not occurred since last read

1 = occurred since last read
3INT_BOR0hSticky bit indicating that brownout condition
0 = did not occurred since last read

1 = occurred since last read
2INT_CLR0hSticky bit indicating that the clock is lost condition
0 = did not occurred since last read

1 = occurred since last read
1INT_SCR0hSticky bit indicating that the SAR complete condition
0 = did not occurred since last read

1 = occurred since last read
0ReservedRW0hReserved

INT_DET_2 (book=0x00 page=0x00 address=0x6C) [reset=0h]

Sticky register used to indicate the source of an interrupt trigger. Register is cleared once read.

Figure 80. INT_DET_2 Register Address: 0x6C
76543210
ReservedReservedReservedReservedINT_CLK1INT_CLK2ReservedReserved
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 58. Interrupt Detected 2 Field Descriptions

BitFieldTypeResetDescription
7ReservedR0hReserved
6ReservedR0hReserved
5ReservedR0hReserved
4ReservedR0hReserved
3INT_CLK1R0hSticky bit indicating that clock error 1 condition
0 = did not occurred since last read

1 = occurred since last read
2INT_CLK2R0hSticky bit indicating that the clock error 2 condition
0 = did not occurred since last read

1 = occurred since last read
1ReservedR0hReserved
0ReservedR0hReserved

LOW_POWER (book=0x00 page=0x00 address=0x79) [reset=0h]

Configures the low power shutdown mode.

Figure 81. LOW_POWER Register Address: 0x79
76543210
VBAT_PORReservedReservedReservedReservedReservedReservedReserved
RW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 59. Lower Power Shutdown Field Descriptions

BitFieldTypeResetDescription
7VBAT_PORRW0hDisable POR and enter lower power mode. The AVDD and VBATT must be present when this mode is used. Low power is
0 = disabled

1 = enabled
6ReservedRW0hReserved
5ReservedRW0hReserved
4ReservedRW0hReserved
3ReservedRW0hReserved
2ReservedRW0hReserved
1ReservedRW0hReserved
0ReservedRW0hReserved

BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]

Book Selection

Figure 82. BOOK Register Address: 0x7F
76543210
BOOK[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 60. Book Selection Field Descriptions

BitFieldTypeResetDescription
7-0BOOK[7:0]RW0hSet the device book
0 = Book 0

1 = Book 1

...

255 = Book 255

PAGE (book=0x00 page=0x01 address=0x00) [reset=1h]

Selects the page for the next read or write.

Figure 83. PAGE Register Address: 0x00
76543210
PAGE[7:0]
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 61. Page Select Field Descriptions

BitFieldTypeResetDescription
7-0PAGE[7:0]RW1hSelects the Register Page for the next read or write command

ASI1_FORMAT (book=0x00 page=0x01 address=0x01) [reset=10h]

Configures the ASI1 format, wordlength, and tristate.

Figure 84. ASI1_FORMAT Register Address: 0x01
76543210
ASI1_MODE[2:0]ASI1_LENGTH[1:0]ReservedASI1_TRISTATE
RW-0hRW-2hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 62. ASI1 Format Field Descriptions

BitFieldTypeResetDescription
7-5ASI1_MODE[2:0]RW0hThe ASI1 Input mode format is set to
0 = I2S

1 = DSP

2 = RJF , For non-zero values of ASI1_OFFSET1, LJF is preferred

3 = LJF

4 = MonoPCM

5-15 = Reserved
4-3ASI1_LENGTH[1:0]RW2hSets the ASI1 input word-length to
0 = 16bits

1 = 20bits

2 = 24bits

3 = 32bits
2-1ReservedRW0hReserved
0ASI1_TRISTATERW0hTri-stating of DOUT for the extra ASI1_BCLK cycles after Data Transfer is over for a frame is
0 = Disabled

1 = Enabled

ASI1_OFFSET_1 (book=0x00 page=0x01 address=0x03) [reset=0h]

Configures the ASI input offset. Offset is measured with respect to WCLK-rising edge in DSP Mode. Offset is not supported for RJF mode

Figure 85. ASI1_OFFSET_1 Register Address: 0x03
76543210
ASI1_OFFSET1[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 63. ASI1 Offset Field Descriptions

BitFieldTypeResetDescription
7-0ASI1_OFFSET1[7:0]RW0hASI1_OFFSET1[7:0]

ASI1_BUSKEEP (book=0x00 page=0x01 address=0x05) [reset=0h]

Configures the buskeeper operation.

Figure 86. ASI1_BUSKEEP Register Address: 0x05
76543210
ASI1_BKPReserved
RW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 64. ASI1 Buskeeper Field Descriptions

BitFieldTypeResetDescription
7ASI1_BKPRW0hBus keep power down when DOUT is tri-stated to save IO power is
0 = disabled

1 = enabled
6-0ReservedRW0hReserved

ASI1_BCLK (book=0x00 page=0x01 address=0x08) [reset=0h]

Configures the bit clock pin, timing, and free running mode

Figure 87. ASI1_BCLK Register Address: 0x08
76543210
ReservedASI1_BCLK[3:0]ReservedASI1_BCTASI1_FRM
RW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 65. ASI1 BCLK Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-3ASI1_BCLK[3:0]RW0hASI1 BCLK input is from
0 = GPIO1 (Preferred pin usage)

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6

6 = GPIO7

7 = GPIO8

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2

14 = GPI3

15-31 = Reserved
2ReservedRW0hReserved
1ASI1_BCTRW0hASI1 BCLK timing as per timing protocol is
0 = normal

1 = inverted
0ASI1_FRMRW0hASI1 BLCK and WCLK are
0 = active in output modes only when ASI1 is active and codec is powered up

1 = is free-running

ASI1_WCLK (book=0x00 page=0x01 address=0x09) [reset=8h]

Configures the word clock pin and timing

Figure 88. ASI1_WCLK Register Address: 0x09
76543210
ReservedASI1_WCLK[3:0]ReservedASI1_WCTReserved
RW-0hRW-1hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 66. ASI1 WCLK Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-3ASI1_WCLK[3:0]RW1hASI1 WCLK input is from
0 = GPIO1

1 = GPIO2 (Preferred pin usage)

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6

6 = GPIO7

7 = GPIO8

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2

14 = GPI3

15-31 = Reserved
2ReservedRW0hReserved
1ASI1_WCTRW0hASI1 WCLK timing as per timing protocol is
0 = normal

1 = inverted
0ReservedRW0hReserved

ASI1_DIN_DOUT (book=0x00 page=0x01 address=0x0C) [reset=0h]

Configures the digital input and output ports.

Figure 89. ASI1_DIN_DOUT Register Address: 0x0C
76543210
ReservedASI1_DIN[3:0]ReservedASI1_DOUT[1:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 67. ASI1 DIN/DOUT Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-3ASI1_DIN[3:0]RW0hASI1 DIN input is from
0 = GPIO1

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6

6 = GPIO7

7 = GPIO8

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1 (Preferred pin usage)

13 = GPI2

14 = GPI3

15-31 = Reserved
2ReservedRW0hReserved
1-0ASI1_DOUT[1:0]RW0hASI1 DOUT output is
0 = DOUT path, output buffer enabled only if i-sense is powered up

1 = ASI1_DIN, loopback

2 = ASI2_DIN, loopback

3 = DOUT path, output buffer enable controlled only based on ASI1 configuration

ASI1_BDIV_CLK (book=0x00 page=0x01 address=0x0D) [reset=1h]

Selects the BDIV clock source

Figure 90. ASI1_BDIV_CLK Register Address: 0x0D
76543210
ReservedASI1_BDIV_SRC[2:0]
RW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 68. ASI1 BDIV Clock Field Descriptions

BitFieldTypeResetDescription
7-3ReservedRW0hReserved
2-0ASI1_BDIV_SRC[2:0]RW1hASI1 bit clock divider (BDIV) source is
0 = NDIV_CLK (Generated On-Chip)

1 = DAC_MOD_CLK (Generated On-Chip)

2 = Reserved

3 = ADC_MOD_CLK (Generated On-Chip)

4 = ASI1_DAC_BCLK (at pin)

5 = Reserved

6 = ASI2_DAC_BCLK (at pin)

7 = Reserved

ASI1_BDIV_RATIO (book=0x00 page=0x01 address=0x0E) [reset=2h]

Configure the BDIV ratio and power.

Figure 91. ASI1_BDIV_RATIO Register Address: 0x0E
76543210
ASI1_BDIV_PWRASI1_BDIV_RTO[6:0]
RW-0hRW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 69. ASI1 BDIV Ratio Field Descriptions

BitFieldTypeResetDescription
7ASI1_BDIV_PWRRW0hThe ASI1 BDIV divider is
0 = powered down

1 = powered up
6-0ASI1_BDIV_RTO[6:0]RW2hThe ASI1 BDIV ratio is
0 = 128

1 = 1

2 = 2

...

126 = 126

127 = 127

ASI1_WDIV_RATIO (book=0x00 page=0x01 address=0x0F) [reset=20h]

Configure the WDIV ratio and power.

Figure 92. ASI1_WDIV_RATIO Register Address: 0x0F
76543210
ASI1_WDIV_PWRASI1_WDIV_RTO[6:0]
RW-0hRW-20h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 70. ASI1 WDIV Ratio Field Descriptions

BitFieldTypeResetDescription
7ASI1_WDIV_PWRRW0hThe ASI1 WDIV divider is
0 = powered down

1 = powered up
6-0ASI1_WDIV_RTO[6:0]RW20hThe ASI1 WDIV ratio is
0 = 128

1 = 1

2 = 2

...

126 = 126

127 = 127

ASI1_CLK_OUT (book=0x00 page=0x01 address=0x10) [reset=0h]

Configures the clock source for BCLK and WCLK

Figure 93. ASI1_CLK_OUT Register Address: 0x10
76543210
ReservedASI1_BCLKS[2:0]ReservedASI1_WCLKS[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 71. ASI1 Clock Source Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4ASI1_BCLKS[2:0]RW0hASI1 bit clock(BCLK) output source is
0 = ASI1 BDIV divider output

1 = ASI1 DAC clock

2 = Reserved

3 = ASI2 BDIV divider output

4 = ASI2 DAC clock

5=15 = Reserved
3ReservedRW0hReserved
2-0ASI1_WCLKS[2:0]RW0hASI1 bit clock(WCLK) output source is
0 = ASI1 WDIV divider output

1 = ASI1 DAC clock

2 = Reserved

3 = ASI2 WDIV divider output

4 = ASI2 DAC clock

5=15 = Reserved

ASI2_FORMAT (book=0x00 page=0x01 address=0x15) [reset=10h]

Configures the ASI2 format, wordlength, and tristate.

Figure 94. ASI2_FORMAT Register Address: 0x15
76543210
ASI2_MODE[2:0]ASI2_LENGTH[1:0]ReservedASI2_TRISTATE
RW-0hRW-2hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 72. ASI2 Format Field Descriptions

BitFieldTypeResetDescription
7-5ASI2_MODE[2:0]RW0hThe ASI1 Input mode format is set to
0 = I2S

1 = DSP

2 = RJF , For non-zero values of ASI2_OFFSET1, LJF is preferred

3 = LJF

4 = MonoPCM

5-15 = Reserved
4-3ASI2_LENGTH[1:0]RW2hSets the ASI2 input word-length to
0 = 16bits

1 = 20bits

2 = 24bits

3 = 32bits
2-1ReservedRW0hReserved
0ASI2_TRISTATERW0hTri-stating of DOUT for the extra ASI2_BCLK cycles after Data Transfer is over for a frame is
0 = Disabled

1 = Enabled

ASI2_OFFSET_1 (book=0x00 page=0x01 address=0x17) [reset=0h]

Configures the ASI input offset. Offset is measured with respect to WCLK-rising edge in DSP Mode. Offset is not supported for RJF mode

Figure 95. ASI2_OFFSET_1 Register Address: 0x17
76543210
ASI2_OFFSET1[7:0]
RW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 73. ASI2 Offset Field Descriptions

BitFieldTypeResetDescription
7-0ASI2_OFFSET1[7:0]RW0hASI2_OFFSET1[7:0]

ASI2_BUSKEEP (book=0x00 page=0x01 address=0x19) [reset=0h]

Configures the buskeeper operation.

Figure 96. ASI2_BUSKEEP Register Address: 0x19
76543210
ASI2_BKPReserved
RW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 74. ASI2 Buskeeper Field Descriptions

BitFieldTypeResetDescription
7ASI2_BKPRW0hBus keep power down when DOUT is tri-stated to save IO power is
0 = disabled

1 = enabled
6-0ReservedRW0hReserved

ASI2_BCLK (book=0x00 page=0x01 address=0x1C) [reset=20h]

Configures the bit clock pin, timing, and free running mode

Figure 97. ASI2_BCLK Register Address: 0x1C
76543210
ReservedASI2_BCLK[3:0]ReservedASI2_BCTASI2_FRM
RW-0hRW-4hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 75. ASI2 BCLK Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-3ASI2_BCLK[3:0]RW4hASI2 BCLK input is from
0 = GPIO1

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5 (Preferred pin usage)

5 = GPIO6

6 = GPIO7

7 = GPIO8

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2

14 = GPI3

15-31 = Reserved
2ReservedRW0hReserved
1ASI2_BCTRW0hASI2 BCLK timing as per timing protocol is
0 = normal

1 = inverted
0ASI2_FRMRW0hASI2 BLCK and WCLK are
0 = active in output modes only when ASI2 is active and codec is powered up

1 = is free-running

ASI2_WCLK (book=0x00 page=0x01 address=0x1D) [reset=28h]

Configures the word clock pin and timing

Figure 98. ASI2_WCLK Register Address: 0x1D
76543210
ReservedASI2_WCLK[3:0]ReservedASI2_WCTReserved
RW-0hRW-5hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 76. ASI2 WCLK Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-3ASI2_WCLK[3:0]RW5hASI2 WCLK input is from
0 = GPIO1

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6 (Preferred pin usage)

6 = GPIO7

7 = GPIO8

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2

14 = GPI3

15-31 = Reserved
2ReservedRW0hReserved
1ASI2_WCTRW0hASI2 WCLK timing as per timing protocol is
0 = normal

1 = inverted
0ReservedRW0hReserved

ASI2_DIN_DOUT (book=0x00 page=0x01 address=0x20) [reset=38h]

Configures the digital input and output ports.

Figure 99. ASI2_DIN_DOUT Register Address: 0x20
76543210
ReservedASI2_DIN[3:0]ReservedASI2_DOUT[1:0]
RW-0hRW-7hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 77. ASI2 DIN/DOUT Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-3ASI2_DIN[3:0]RW7hASI2 DIN input is from
0 = GPIO1

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6

6 = GPIO7

7 = GPIO8 (Preferred pin usage)

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2

14 = GPI3

15-31 = Reserved
2ReservedRW0hReserved
1-0ASI2_DOUT[1:0]RW0hASI2 DOUT output is
0 = DOUT path, output buffer enabled only if i-sense is powered up

1 = ASI1_DIN, loopback

2 = ASI2_DIN, loopback

3 = DOUT path, output buffer enable controlled only based on ASI1 configuration

ASI2_BDIV_CLK (book=0x00 page=0x01 address=0x21) [reset=1h]

Selects the BDIV clock source

Figure 100. ASI2_BDIV_CLK Register Address: 0x21
76543210
ReservedASI2_BDIV_SRC[2:0]
RW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 78. ASI2 BDIV Clock Field Descriptions

BitFieldTypeResetDescription
7-3ReservedRW0hReserved
2-0ASI2_BDIV_SRC[2:0]RW1hASI1 bit clock divider (BDIV) source is
0 = NDIV_CLK (Generated On-Chip)

1 = DAC_MOD_CLK (Generated On-Chip)

2 = Reserved

3 = ADC_MOD_CLK (Generated On-Chip)

4 = ASI1_DAC_BCLK (at pin)

5 = Reserved

6 = ASI2_DAC_BCLK (at pin)

7 = Reserved

ASI2_BDIV_RATIO (book=0x00 page=0x01 address=0x22) [reset=2h]

Configure the BDIV ratio and power.

Figure 101. ASI2_BDIV_RATIO Register Address: 0x22
76543210
ASI2_BDIV_PWRASI2_BDIV_RTO[6:0]
RW-0hRW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 79. ASI2 BDIV Ratio Field Descriptions

BitFieldTypeResetDescription
7ASI2_BDIV_PWRRW0hThe ASI2 BDIV divider is
0 = powered down

1 = powered up
6-0ASI2_BDIV_RTO[6:0]RW2hThe ASI2 BDIV ratio is
0 = 128

1 = 1

2 = 2

...

126 = 126

127 = 127

ASI2_WDIV_RATIO (book=0x00 page=0x01 address=0x23) [reset=20h]

Configure the WDIV ratio and power.

Figure 102. ASI2_WDIV_RATIO Register Address: 0x23
76543210
ASI2_WDIV_PWRASI2_WDIV_RTO[6:0]
RW-0hRW-20h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 80. ASI2 WDIV Ratio Field Descriptions

BitFieldTypeResetDescription
7ASI2_WDIV_PWRRW0hThe ASI2 WDIV divider is
0 = powered down

1 = powered up
6-0ASI2_WDIV_RTO[6:0]RW20hThe ASI2 WDIV ratio is
0 = 128

1 = 1

2 = 2

...

126 = 126

127 = 127

ASI2_CLK_OUT (book=0x00 page=0x01 address=0x24) [reset=33h]

Configures the clock source for BCLK and WCLK

Figure 103. ASI2_CLK_OUT Register Address: 0x24
76543210
ReservedASI2_BCLKS[2:0]ReservedASI2_WCLKS[2:0]
RW-0hRW-3hRW-0hRW-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 81. ASI2 Clock Source Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4ASI2_BCLKS[2:0]RW3hASI2 bit clock(BCLK) output source is
0 = ASI1 BDIV divider output

1 = ASI1 DAC clock

2 = Reserved

3 = ASI2 BDIV divider output

4 = ASI2 DAC clock

5=15 = Reserved
3ReservedRW0hReserved
2-0ASI2_WCLKS[2:0]RW3hASI2 bit clock(WCLK) output source is
0 = ASI1 WDIV divider output

1 = ASI1 DAC clock

2 = Reserved

3 = ASI2 WDIV divider output

4 = ASI2 DAC clock

5=15 = Reserved

GPIO1_PIN (book=0x00 page=0x01 address=0x3D) [reset=1h]

Configures BCLK1_GPIO1 pin.

Figure 104. GPIO1_PIN Register Address: 0x3D
76543210
ReservedGP1_VALReservedGP1_OUT[4:0]
RW-0hRW-0hRW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 82. GPIO1 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GP1_VALRW0hWhen value GP1_OUT=3, configure pin output to
0 = Low

1 = High
5ReservedRW0hReserved
4-0GP1_OUT[4:0]RW1hPin is configured to
0 = disabled, buffers powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = output, use GP1_VAL to set value

4 = output, use GPBB_VAL to set value

5 = output, PDM clk output for PDM data input

6 = output, CLKOUT output

7 = output, INT1 interrupt

8 = output, INT2 interrupt

9 = output, INT3 interrupt

10 = output, INT4 interrupt

11 = Reserved

12 = output, ASI1_WCLK_OUT

13 = output, ASI1_BCLK_OUT

14-15 = Reserved

16 = ASI1_DOUT

17 = ASI1_WCLK_OUT

18 = ASI2_BCLK_OUT

19-20 = Reserved

21 = ASI2_DOUT

22-26 = Reserved

27 = ASIM_WCLK_OUT

28 = ASIM_BCLK_OUT

29 = ASIM_DOUT

30-31 = Reserved

GPIO2_PIN (book=0x00 page=0x01 address=0x3E) [reset=1h]

Configures WCLK1_GPIO2 pin.

Figure 105. GPIO2_PIN Register Address: 0x3E
76543210
ReservedGP2_VALReservedGP2_OUT[4:0]
RW-0hRW-0hRW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 83. GPIO2 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GP2_VALRW0hWhen value GP2_OUT=3, configure pin output to
0 = Low

1 = High
5ReservedRW0hReserved
4-0GP2_OUT[4:0]RW1hPin is configured to
0 = disabled, buffers powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = output, use GP2_VAL to set value

4 = output, use GPBB_VAL to set value

5 = output, PDM clk output for PDM data input

6 = output, CLKOUT output

7 = output, INT1 interrupt

8 = output, INT2 interrupt

9 = output, INT3 interrupt

10 = output, INT4 interrupt

11 = Reserved

12 = output, ASI1_WCLK_OUT

13 = output, ASI1_BCLK_OUT

14-15 = Reserved

16 = ASI1_DOUT

17 = ASI1_WCLK_OUT

18 = ASI2_BCLK_OUT

19-20 = Reserved

21 = ASI2_DOUT

22-26 = Reserved

27 = ASIM_WCLK_OUT

28 = ASIM_BCLK_OUT

29 = ASIM_DOUT

30-31 = Reserved

GPIO3_PIN (book=0x00 page=0x01 address=0x3F) [reset=10h]

Configures DOUT1_GPIO3 pin.

Figure 106. GPIO3_PIN Register Address: 0x3F
76543210
ReservedGP3_VALReservedGP3_OUT[4:0]
RW-0hRW-0hRW-0hRW-10h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 84. GPIO3 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GP3_VALRW0hWhen value GP3_OUT=3, configure pin output to
0 = Low

1 = High
5ReservedRW0hReserved
4-0GP3_OUT[4:0]RW10hPin is configured to
0 = disabled, buffers powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = output, use GP3_VAL to set value

4 = output, use GPBB_VAL to set value

5 = output, PDM clk output for PDM data input

6 = output, CLKOUT output

7 = output, INT1 interrupt

8 = output, INT2 interrupt

9 = output, INT3 interrupt

10 = output, INT4 interrupt

11 = Reserved

12 = output, ASI1_WCLK_OUT

13 = output, ASI1_BCLK_OUT

14-15 = Reserved

16 = ASI1_DOUT

17 = ASI1_WCLK_OUT

18 = ASI2_BCLK_OUT

19-20 = Reserved

21 = ASI2_DOUT

22-26 = Reserved

27 = ASIM_WCLK_OUT

28 = ASIM_BCLK_OUT

29 = ASIM_DOUT

30-31 = Reserved

GPIO4_PIN (book=0x00 page=0x01 address=0x40) [reset=7h]

Configures IRQ_GPIO4 pin.

Figure 107. GPIO4_PIN Register Address: 0x40
76543210
ReservedGP4_VALReservedGP4_OUT[4:0]
RW-0hRW-0hRW-0hRW-7h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 85. GPIO4 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GP4_VALRW0hWhen value GP4_OUT=3, configure pin output to
0 = Low

1 = High
5ReservedRW0hReserved
4-0GP4_OUT[4:0]RW7hPin is configured to
0 = disabled, buffers powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = output, use GP4_VAL to set value

4 = output, use GPBB_VAL to set value

5 = output, PDM clk output for PDM data input

6 = output, CLKOUT output

7 = output, INT1 interrupt

8 = output, INT2 interrupt

9 = output, INT3 interrupt

10 = output, INT4 interrupt

11 = Reserved

12 = output, ASI1_WCLK_OUT

13 = output, ASI1_BCLK_OUT

14-15 = Reserved

16 = ASI1_DOUT

17 = ASI1_WCLK_OUT

18 = ASI2_BCLK_OUT

19-20 = Reserved

21 = ASI2_DOUT

22-26 = Reserved

27 = ASIM_WCLK_OUT

28 = ASIM_BCLK_OUT

29 = ASIM_DOUT

30-31 = Reserved

GPIO5_PIN (book=0x00 page=0x01 address=0x41) [reset=0h]

Configures BCLK2_GPIO5 pin.

Figure 108. GPIO5_PIN Register Address: 0x41
76543210
ReservedGP5_VALReservedGP5_OUT[4:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 86. GPIO5 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GP5_VALRW0hWhen value GP5_OUT=3, configure pin output to
0 = Low

1 = High
5ReservedRW0hReserved
4-0GP5_OUT[4:0]RW0hPin is configured to
0 = disabled, buffers powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = output, use GP5_VAL to set value

4 = output, use GPBB_VAL to set value

5 = output, PDM clk output for PDM data input

6 = output, CLKOUT output

7 = output, INT1 interrupt

8 = output, INT2 interrupt

9 = output, INT3 interrupt

10 = output, INT4 interrupt

11 = Reserved

12 = output, ASI1_WCLK_OUT

13 = output, ASI1_BCLK_OUT

14-15 = Reserved

16 = ASI1_DOUT

17 = ASI1_WCLK_OUT

18 = ASI2_BCLK_OUT

19-20 = Reserved

21 = ASI2_DOUT

22-26 = Reserved

27 = ASIM_WCLK_OUT

28 = ASIM_BCLK_OUT

29 = ASIM_DOUT

30-31 = Reserved

GPIO6_PIN (book=0x00 page=0x01 address=0x42) [reset=0h]

Configures WCLK2_GPIO6 pin.

Figure 109. GPIO6_PIN Register Address: 0x42
76543210
ReservedGP6_VALReservedGP6_OUT[4:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 87. GPIO6 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GP6_VALRW0hWhen value GP6_OUT=3, configure pin output to
0 = Low

1 = High
5ReservedRW0hReserved
4-0GP6_OUT[4:0]RW0hPin is configured to
0 = disabled, buffers powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = output, use GP6_VAL to set value

4 = output, use GPBB_VAL to set value

5 = output, PDM clk output for PDM data input

6 = output, CLKOUT output

7 = output, INT1 interrupt

8 = output, INT2 interrupt

9 = output, INT3 interrupt

10 = output, INT4 interrupt

11 = Reserved

12 = output, ASI1_WCLK_OUT

13 = output, ASI1_BCLK_OUT

14-15 = Reserved

16 = ASI1_DOUT

17 = ASI1_WCLK_OUT

18 = ASI2_BCLK_OUT

19-20 = Reserved

21 = ASI2_DOUT

22-26 = Reserved

27 = ASIM_WCLK_OUT

28 = ASIM_BCLK_OUT

29 = ASIM_DOUT

30-31 = Reserved

GPIO7_PIN (book=0x00 page=0x01 address=0x43) [reset=0h]

Configures DOUT2_GPIO7 pin.

Figure 110. GPIO7_PIN Register Address: 0x43
76543210
ReservedGP7_VALReservedGP7_OUT[4:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 88. GPIO7 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GP7_VALRW0hWhen value GP7_OUT=3, configure pin output to
0 = Low

1 = High
5ReservedRW0hReserved
4-0GP7_OUT[4:0]RW0hPin is configured to
0 = disabled, buffers powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = output, use GP7_VAL to set value

4 = output, use GPBB_VAL to set value

5 = output, PDM clk output for PDM data input

6 = output, CLKOUT output

7 = output, INT1 interrupt

8 = output, INT2 interrupt

9 = output, INT3 interrupt

10 = output, INT4 interrupt

11 = Reserved

12 = output, ASI1_WCLK_OUT

13 = output, ASI1_BCLK_OUT

14-15 = Reserved

16 = ASI1_DOUT

17 = ASI1_WCLK_OUT

18 = ASI2_BCLK_OUT

19-20 = Reserved

21 = ASI2_DOUT

22-26 = Reserved

27 = ASIM_WCLK_OUT

28 = ASIM_BCLK_OUT

29 = ASIM_DOUT

30-31 = Reserved

GPIO8_PIN (book=0x00 page=0x01 address=0x44) [reset=0h]

Configures DIN2_GPIO8 pin.

Figure 111. GPIO8_PIN Register Address: 0x44
76543210
ReservedGP8_VALReservedGP8_OUT[4:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 89. GPIO8 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GP8_VALRW0hWhen value GP8_OUT=3, configure pin output to
0 = Low

1 = High
5ReservedRW0hReserved
4-0GP8_OUT[4:0]RW0hPin is configured to
0 = disabled, buffers powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = output, use GP8_VAL to set value

4 = output, use GPBB_VAL to set value

5 = output, PDM clk output for PDM data input

6 = output, CLKOUT output

7 = output, INT1 interrupt

8 = output, INT2 interrupt

9 = output, INT3 interrupt

10 = output, INT4 interrupt

11 = Reserved

12 = output, ASI1_WCLK_OUT

13 = output, ASI1_BCLK_OUT

14-15 = Reserved

16 = ASI1_DOUT

17 = ASI1_WCLK_OUT

18 = ASI2_BCLK_OUT

19-20 = Reserved

21 = ASI2_DOUT

22-26 = Reserved

27 = ASIM_WCLK_OUT

28 = ASIM_BCLK_OUT

29 = ASIM_DOUT

30-31 = Reserved

GPIO9_PIN (book=0x00 page=0x01 address=0x45) [reset=0h]

Configures ICC_CLK_GPIO9 pin.

Figure 112. GPIO9_PIN Register Address: 0x45
76543210
ReservedGP9_VALReservedGP9_OUT[4:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 90. GPIO9 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GP9_VALRW0hWhen value GP9_OUT=3, configure pin output to
0 = Low

1 = High
5ReservedRW0hReserved
4-0GP9_OUT[4:0]RW0hPin is configured to
0 = disabled, buffers powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = output, use GP9_VAL to set value

4 = output, use GPBB_VAL to set value

5 = output, PDM clk output for PDM data input

6 = output, CLKOUT output

7 = output, INT1 interrupt

8 = output, INT2 interrupt

9 = output, INT3 interrupt

10 = output, INT4 interrupt

11 = Reserved

12 = output, ASI1_WCLK_OUT

13 = output, ASI1_BCLK_OUT

14-15 = Reserved

16 = ASI1_DOUT

17 = ASI1_WCLK_OUT

18 = ASI2_BCLK_OUT

19-20 = Reserved

21 = ASI2_DOUT

22-26 = Reserved

27 = ASIM_WCLK_OUT

28 = ASIM_BCLK_OUT

29 = ASIM_DOUT

30-31 = Reserved

GPIO10_PIN (book=0x00 page=0x01 address=0x46) [reset=0h]

Configures ICC_DOUT_GPIO10 pin.

Figure 113. GPIO10_PIN Register Address: 0x46
76543210
ReservedGP10_VALReservedGP10_OUT[4:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 91. GPIO10 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6GP10_VALRW0hWhen value GP10_OUT=3, configure pin output to
0 = Low

1 = High
5ReservedRW0hReserved
4-0GP10_OUT[4:0]RW0hPin is configured to
0 = disabled, buffers powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = output, use GP10_VAL to set value

4 = output, use GPBB_VAL to set value

5 = output, PDM clk output for PDM data input

6 = output, CLKOUT output

7 = output, INT1 interrupt

8 = output, INT2 interrupt

9 = output, INT3 interrupt

10 = output, INT4 interrupt

11 = Reserved

12 = output, ASI1_WCLK_OUT

13 = output, ASI1_BCLK_OUT

14-15 = Reserved

16 = ASI1_DOUT

17 = ASI1_WCLK_OUT

18 = ASI2_BCLK_OUT

19-20 = Reserved

21 = ASI2_DOUT

22-26 = Reserved

27 = ASIM_WCLK_OUT

28 = ASIM_BCLK_OUT

29 = ASIM_DOUT

30-31 = Reserved

GPI_PIN (book=0x00 page=0x01 address=0x4D) [reset=0h]

Configures the GPI pins

Figure 114. GPI_PIN Register Address: 0x4D
76543210
ReservedGPI3_MODE[1:0]GPI2_MODE[1:0]GPI1_MODE[1:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 92. GPI Pin Mode Field Descriptions

BitFieldTypeResetDescription
7-6ReservedRW0hReserved
5-4GPI3_MODE[1:0]RW0hPin GPI3 mode is
0 = disabled, powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = Reserved
3-2GPI2_MODE[1:0]RW0hPin GPI2 mode is
0 = disabled, powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = Reserved
1-0GPI1_MODE[1:0]RW0hPin GPI1 mode is
0 = disabled, powered down

1 = input, use input MUX for relevant function

2 = Reserved

3 = Reserved

GPIO_HIZ_1 (book=0x00 page=0x01 address=0x4F) [reset=0h]

Configures high-Z state of GPIO1 and GPIO2

Figure 115. GPIO_HIZ_1 Register Address: 0x4F
76543210
ReservedGP2_HIZ[2:0]ReservedGP1_HIZ[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 93. GPIO HiZ 1 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4GP2_HIZ[2:0]RW0hPin GPIO2 output is
0 = driven both LO/HI

1 = driven both LO/HI with buskeeper for use with outputs needing tri-stated

2 = Reserved

3 = Reserved

4 = Reserved

5 = Reserved

6 = Reserved

7 = Reserved
3ReservedRW0hReserved
2-0GP1_HIZ[2:0]RW0hPin GPIO1 output is
0 = driven both LO/HI

1 = driven both LO/HI with buskeeper for use with outputs needing tri-stated

2 = Reserved

3 = Reserved

4 = Reserved

5 = Reserved

6 = Reserved

7 = Reserved

GPIO_HIZ_2 (book=0x00 page=0x01 address=0x50) [reset=0h]

Configures high-Z state of GPIO3 and GPIO4

Figure 116. GPIO_HIZ_2 Register Address: 0x50
76543210
ReservedGP4_HIZ[2:0]ReservedGP3_HIZ[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 94. GPIO HiZ 2 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4GP4_HIZ[2:0]RW0hPin GPIO4 output is
0 = driven both LO/HI

1 = driven both LO/HI with buskeeper for use with outputs needing tri-stated

2 = Reserved

3 = Reserved

4 = Reserved

5 = Reserved

6 = Reserved

7 = Reserved
3ReservedRW0hReserved
2-0GP3_HIZ[2:0]RW0hPin GPIO3 output is
0 = driven both LO/HI

1 = driven both LO/HI with buskeeper for use with outputs needing tri-stated

2 = Reserved

3 = Reserved

4 = Reserved

5 = Reserved

6 = Reserved

7 = Reserved

GPIO_HIZ_3 (book=0x00 page=0x01 address=0x51) [reset=0h]

Configures high-Z state of GPIO5 and GPIO6

Figure 117. GPIO_HIZ_3 Register Address: 0x51
76543210
ReservedGP6_HIZ[2:0]ReservedGP5_HIZ[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 95. GPIO HiZ 3 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4GP6_HIZ[2:0]RW0hPin GPIO6 output is
0 = driven both LO/HI

1 = driven both LO/HI with buskeeper for use with outputs needing tri-stated

2 = Reserved

3 = Reserved

4 = Reserved

5 = Reserved

6 = Reserved

7 = Reserved
3ReservedRW0hReserved
2-0GP5_HIZ[2:0]RW0hPin GPIO5 output is
0 = driven both LO/HI

1 = driven both LO/HI with buskeeper for use with outputs needing tri-stated

2 = Reserved

3 = Reserved

4 = Reserved

5 = Reserved

6 = Reserved

7 = Reserved

GPIO_HIZ_4 (book=0x00 page=0x01 address=0x52) [reset=0h]

Configures high-Z state of GPIO7 and GPIO8

Figure 118. GPIO_HIZ_4 Register Address: 0x52
76543210
ReservedGP8_HIZ[2:0]ReservedGP7_HIZ[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 96. GPIO HiZ 4 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4GP8_HIZ[2:0]RW0hPin GPIO8 output is
0 = driven both LO/HI

1 = driven both LO/HI with buskeeper for use with outputs needing tri-stated

2 = Reserved

3 = Reserved

4 = Reserved

5 = Reserved

6 = Reserved

7 = Reserved
3ReservedRW0hReserved
2-0GP7_HIZ[2:0]RW0hPin GPIO7 output is
0 = driven both LO/HI

1 = driven both LO/HI with buskeeper for use with outputs needing tri-stated

2 = Reserved

3 = Reserved

4 = Reserved

5 = Reserved

6 = Reserved

7 = Reserved

GPIO_HIZ_5 (book=0x00 page=0x01 address=0x53) [reset=0h]

Configures high-Z state of GPIO9 and GPIO10

Figure 119. GPIO_HIZ_5 Register Address: 0x53
76543210
ReservedGP10_HIZ[2:0]ReservedGP9_HIZ[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 97. GPIO HiZ 5 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4GP10_HIZ[2:0]RW0hPin GPIO10 output is
0 = driven both LO/HI

1 = driven both LO/HI with buskeeper for use with outputs needing tri-stated

2 = Reserved

3 = Reserved

4 = Reserved

5 = Reserved

6 = Reserved

7 = Reserved
3ReservedRW0hReserved
2-0GP9_HIZ[2:0]RW0hPin GPIO9 output is
0 = driven both LO/HI

1 = driven both LO/HI with buskeeper for use with outputs needing tri-stated

2 = Reserved

3 = Reserved

4 = Reserved

5 = Reserved

6 = Reserved

7 = Reserved

BIT_BANG_OUT1 (book=0x00 page=0x01 address=0x58) [reset=0h]

GPIO pin state when using bit-bang output.

Figure 120. BIT_BANG_OUT1 Register Address: 0x58
76543210
BBO_GP8BBO_GP7BBO_GP6BBO_GP5BBO_GP4BBO_GP3BBO_GP2BBO_GP1
RW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 98. Bit Bang Output 1 Field Descriptions

BitFieldTypeResetDescription
7BBO_GP8RW0hGPIO8 pin output is
0 = low

1 = high
6BBO_GP7RW0hGPIO7 pin output is
0 = low

1 = high
5BBO_GP6RW0hGPIO6 pin output is
0 = low

1 = high
4BBO_GP5RW0hGPIO5 pin output is
0 = low

1 = high
3BBO_GP4RW0hGPIO4 pin output is
0 = low

1 = high
2BBO_GP3RW0hGPIO3 pin output is
0 = low

1 = high
1BBO_GP2RW0hGPIO2 pin output is
0 = low

1 = high
0BBO_GP1RW0hGPIO1 pin output is
0 = low

1 = high

BIT_BANG_OUT2 (book=0x00 page=0x01 address=0x59) [reset=0h]

GPIO pin state when using pin as bit-bang output.

Figure 121. BIT_BANG_OUT2 Register Address: 0x59
76543210
ReservedBBO_GP10BBO_GP9
RW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 99. Bit Bang Output 2 Field Descriptions

BitFieldTypeResetDescription
7-2ReservedRW0hReserved
1BBO_GP10RW0hGPIO10 pin output is
0 = low

1 = high
0BBO_GP9RW0hGPIO9 pin output is
0 = low

1 = high

BIT_BANG_IN1 (book=0x00 page=0x01 address=0x5A) [reset=0h]

GPIO pin value when used as bit-bang input.

Figure 122. BIT_BANG_IN1 Register Address: 0x5A
76543210
BBI_GP8BBI_GP7BBI_GP6BBI_GP5BBI_GP4BBI_GP3BBI_GP2BBI_GP1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 100. Bit Bang Input 1 Field Descriptions

BitFieldTypeResetDescription
7BBI_GP8R0hGPIO8 pin input is
0 = low

1 = high
6BBI_GP7R0hGPIO7 pin input is
0 = low

1 = high
5BBI_GP6R0hGPIO6 pin input is
0 = low

1 = high
4BBI_GP5R0hGPIO5 pin input is
0 = low

1 = high
3BBI_GP4R0hGPIO4 pin input is
0 = low

1 = high
2BBI_GP3R0hGPIO3 pin input is
0 = low

1 = high
1BBI_GP2R0hGPIO2 pin input is
0 = low

1 = high
0BBI_GP1R0hGPIO1 pin input is
0 = low

1 = high

BIT_BANG_IN2 (book=0x00 page=0x01 address=0x5B) [reset=0h]

GPIO pin value when used as bit-bang input.

Figure 123. BIT_BANG_IN2 Register Address: 0x5B
76543210
ReservedBBI_GP10BBI_GP9
RW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 101. Bit Bang Input 2 Field Descriptions

BitFieldTypeResetDescription
7-2ReservedRW0hReserved
1BBI_GP10RW0hGPIO10 pin input is
0 = low

1 = high
0BBI_GP9RW0hGPIO9 pin input is
0 = low

1 = high

BIT_BANG_IN3 (book=0x00 page=0x01 address=0x5C) [reset=0h]

GPI pin value when used as bit-bang input.

Figure 124. BIT_BANG_IN3 Register Address: 0x5C
76543210
ReservedBBI_GPI3BBI_GPI2BBI_GPI1
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 102. Bit Bang Input 3 Field Descriptions

BitFieldTypeResetDescription
7-3ReservedRW0hReserved
2BBI_GPI3RW0hGPI3 pin input is
0 = low

1 = high
1BBI_GPI2RW0hGPI2 pin input is
0 = low

1 = high
0BBI_GPI1RW0hGPI1 pin input is
0 = low

1 = high

ASIM_BUSKEEP (book=0x00 page=0x01 address=0x60) [reset=0h]

Configures the buskeeper operation.

Figure 125. ASIM_BUSKEEP Register Address: 0x60
76543210
ASIM_BKPReserved
RW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 103. ASIM Buskeeper Field Descriptions

BitFieldTypeResetDescription
7ASIM_BKPRW0hBus keep power down when DOUT is tri-stated to save IO power is
0 = disabled

1 = enabled
6-0ReservedRW0hReserved

ASIM_MODE (book=0x00 page=0x01 address=0x61) [reset=8h]

specifies the format and slots for the Interchip Communication (ICC) Interface

Figure 126. ASIM_MODE Register Address: 0x61
76543210
ASIM_INTReservedASIM_WCNT[3:0]ASIM_RSASIM_WS
RW-0hRW-0hRW-2hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 104. ASIM Mode Field Descriptions

BitFieldTypeResetDescription
7ASIM_INTRW0hASIM interface is
0 = Non-ICC set by ASIM_FORMAT

1 = ICC interface for multichip
6ReservedRW0hReserved
5-2ASIM_WCNT[3:0]RW2hThe number of words(32-bit samples) in one frame of the ICC. The total number of bit transmissed is (1+words)*33
0 = Reserved

1 = 1 word

2 = 2 words

...

13 = 13 words

14 = 14 words

15 = Reserved
1ASIM_RSRW0hThe device will read the following ICC slots and transfer data to DSP
0 = only it own slot

1 = all slots
0ASIM_WSRW0hThe device will write the following ICC slots and transfer data to DSP
0 = only it own slot

1 = all slots

ASIM_NUM_DEV (book=0x00 page=0x01 address=0x62) [reset=0h]

specifies the number of devices on the Interchip Communication (ICC) Interface

Figure 127. ASIM_NUM_DEV Register Address: 0x62
76543210
ReservedASIM_TND[2:0]ReservedASIM_DN[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 105. ASIM Number Devices Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4ASIM_TND[2:0]RW0hTotal number of devices on the ICC interface bus
0 = 8

1 = 1

2 = 2

...

6 = 6

7 = 7
3ReservedRW0hReserved
2-0ASIM_DN[2:0]RW0hThe device number for this device on the ICC interface bus
0 = 1

1 = 2

...

6 = 7

7 = 8

ASIM_FORMAT (book=0x00 page=0x01 address=0x63) [reset=10h]

Configures the ASI2 format, wordlength, and tristate.

Figure 128. ASIM_FORMAT Register Address: 0x63
76543210
ASIM_MODE[2:0]ASI2_LENGTH[1:0]ReservedASI2_TRISTATE
RW-0hRW-2hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 106. ASIM Format Field Descriptions

BitFieldTypeResetDescription
7-5ASIM_MODE[2:0]RW0hThe ASIM Input mode format is set to
0 = I2S

1 = DSP

2 = RJF , For non-zero values of ASIM_OFFSET1, LJF is preferred

3 = LJF

4 = MonoPCM

5-15 = Reserved
4-3ASI2_LENGTH[1:0]RW2hSets the ASIM input word-length to
0 = 16bits

1 = 20bits

2 = 24bits

3 = 32bits
2-1ReservedRW0hReserved
0ASI2_TRISTATERW0hTri-stating of DOUT for the extra ASIM_BCLK cycles after Data Transfer is over for a frame is
0 = Disabled

1 = Enabled

ASIM_BDIV_CLK (book=0x00 page=0x01 address=0x64) [reset=1h]

Selects the BDIV clock source and input/output mode for WCLK/BCLK.

Figure 129. ASIM_BDIV_CLK Register Address: 0x64
76543210
ASIM_BCDASIM_WCDReservedASIM_BDIV_SRC[2:0]
RW-0hRW-0hRW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 107. ASIM BDIV Clock Field Descriptions

BitFieldTypeResetDescription
7ASIM_BCDRW0hASIM BCLK is
0 = input

1 = output; use only in ICC mode if device number is 1
6ASIM_WCDRW0hASIM WCLK is
0 = input

1 = output
5-3ReservedRW0hReserved
2-0ASIM_BDIV_SRC[2:0]RW1hASIM bit clock divider (BDIV) source is
0 = NDIV_CLK (Generated On-Chip)

1 = DAC_MOD_CLK (Generated On-Chip)

2 = Reserved

3 = ADC_MOD_CLK (Generated On-Chip)

4 = ASI1_DAC_BCLK (at pin)

5 = ASI1_ADC_BLKC (at pin)

6 = ASI2_DAC_BCLK (at pin)

7 = ASI2_ADC_BCLK (at pin)

ASIM_BDIV_RATIO (book=0x00 page=0x01 address=0x65) [reset=2h]

Configure the BDIV ratio and power.

Figure 130. ASIM_BDIV_RATIO Register Address: 0x65
76543210
ASIM_BDIV_PWRASIM_BDIV_RTO[6:0]
RW-0hRW-2h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 108. ASIM BDIV Ratio Field Descriptions

BitFieldTypeResetDescription
7ASIM_BDIV_PWRRW0hThe ASIM BDIV divider is
0 = powered down

1 = powered up
6-0ASIM_BDIV_RTO[6:0]RW2hThe ASIM BDIV ratio is
0 = 128

1 = 1

2 = 2

...

126 = 126

127 = 127

ASIM_WDIV_RATIO_1 (book=0x00 page=0x01 address=0x66) [reset=0h]

Configure the WDIV ratio and power.

Figure 131. ASIM_WDIV_RATIO_1 Register Address: 0x66
76543210
ASIM_WDIV_PWRReservedASIM_WDIV_RTO[9:8]
RW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 109. ASIM WDIV Ratio Field Descriptions

BitFieldTypeResetDescription
7ASIM_WDIV_PWRRW0hThe ASIM WDIV divider is
0 = powered down

1 = powered up
6-2ReservedRW0hReserved
1--8ASIM_WDIV_RTO[9:0]RW0hMSB for ASIM WDIV divider

ASIM_WDIV_RATIO_2 (book=0x00 page=0x01 address=0x67) [reset=20h]

Configure the WDIV ratio.

Figure 132. ASIM_WDIV_RATIO_2 Register Address: 0x67
76543210
ASIM_WDIV_RTO[7:0]
RW-20h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 110. ASIM WDIV Ratio Field Descriptions

BitFieldTypeResetDescription
7-0ASIM_WDIV_RTO[7:0]RW20hLSB for ASIM WDIV. Number for ASIM_BDIV clock cycles in on ASIM_WCLK frame
0 = 1024

1 = 1

2 = 2

...

1022 = 1022

1023 = 1023

ASIM_BCLK (book=0x00 page=0x01 address=0x68) [reset=40h]

Configures the bit clock pin.

Figure 133. ASIM_BCLK Register Address: 0x68
76543210
ReservedASI1_BCLK[3:0]Reserved
RW-0hRW-8hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 111. ASI1 BCLK Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-3ASI1_BCLK[3:0]RW8hASIM BCLK input is from
0 = GPIO1

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6

6 = GPIO7

7 = GPIO8

8 = GPIO9 (Preferred pin usage)

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2

14 = GPI3

15-31 = Reserved
2-0ReservedRW0hReserved

ASIM_WCLK (book=0x00 page=0x01 address=0x69) [reset=38h]

Configures the word clock pin.

Figure 134. ASIM_WCLK Register Address: 0x69
76543210
ReservedASIM_WCLK[3:0]Reserved
RW-0hRW-7hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 112. ASI1 WCLK Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-3ASIM_WCLK[3:0]RW7hASIM BCLK input is from
0 = GPIO1

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6

6 = GPIO7

7 = GPIO8 (Preferred pin usage)

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2

14 = GPI3

15-31 = Reserved
2-0ReservedRW0hReserved

ASIM_DIN (book=0x00 page=0x01 address=0x6A) [reset=70h]

Configures the ASIM data input pin and clock detection 2 interrupt generation.

Figure 135. ASIM_DIN Register Address: 0x6A
76543210
ReservedASIM_DIN[3:0]INT_GEN_CH2[2:0]
RW-0hRW-EhRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 113. ASI1 DIN Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-3ASIM_DIN[3:0]RWEhASIM BCLK input is from
0 = GPIO1

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6

6 = GPIO7

7 = GPIO8

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2

14 = GPI3 (Preferred pin usage)

15-31 = Reserved
2-0INT_GEN_CH2[2:0]RW0hClock halt detection 2 is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved

INT_GEN_1 (book=0x00 page=0x01 address=0x6C) [reset=0h]

Assign speaker over-current and device over-voltage to specific interrupt

Figure 136. INT_GEN_1 Register Address: 0x6C
76543210
ReservedINT_GEN_OC[2:0]ReservedINT_GEN_OV[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 114. Interrupt Generation 1 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4INT_GEN_OC[2:0]RW0hSpeaker over current is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved
3ReservedRW0hReserved
2-0INT_GEN_OV[2:0]RW0hDevice over voltage is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved

INT_GEN_2 (book=0x00 page=0x01 address=0x6D) [reset=0h]

Assign clock error deteciton 1 and die over temperature to specific interrupt

Figure 137. INT_GEN_2 Register Address: 0x6D
76543210
ReservedINT_GEN_CE1[2:0]ReservedINT_GEN_OT[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 115. Interrupt Generation 2 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4INT_GEN_CE1[2:0]RW0hClock error detection 1 is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved
3ReservedRW0hReserved
2-0INT_GEN_OT[2:0]RW0hDie over-temperature is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved

INT_GEN_3 (book=0x00 page=0x01 address=0x6E) [reset=0h]

Assign clock error deteciton 2 and brownout to specific interrupt

Figure 138. INT_GEN_3 Register Address: 0x6E
76543210
ReservedINT_GEN_BO[2:0]ReservedINT_GEN_CE2[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 116. Interrupt Generation 3 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4INT_GEN_BO[2:0]RW0hDevice brownout is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved
3ReservedRW0hReserved
2-0INT_GEN_CE2[2:0]RW0hClock error detection 2 is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved

INT_GEN_4 (book=0x00 page=0x01 address=0x6F) [reset=0h]

Assign SAR complete and clock halt 1 to specific interrupt

Figure 139. INT_GEN_4 Register Address: 0x6F
76543210
ReservedINT_GEN_SC[2:0]ReservedINT_GEN_CL[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 117. Interrupt Generation 4 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4INT_GEN_SC[2:0]RW0hSAR measurement complete is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved
3ReservedRW0hReserved
2-0INT_GEN_CL[2:0]RW0hClock lost halt 1 is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved

INT_GEN_5 (book=0x00 page=0x01 address=0x70) [reset=0h]

Assign DSP Interrupt 1 and DSP interrupt 2 to specific interrupt

Figure 140. INT_GEN_5 Register Address: 0x70
76543210
ReservedINT_GEN_DSP1[2:0]ReservedINT_GEN_DSP2[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 118. Interrupt Generation 5 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4INT_GEN_DSP1[2:0]RW0hDSP output interrupt 1 is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved
3ReservedRW0hReserved
2-0INT_GEN_DSP2[2:0]RW0hDSP output interrupt 2 is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved

INT_GEN_6 (book=0x00 page=0x01 address=0x71) [reset=0h]

Assign DSP Interrupt 3 and DSP interrupt 4 to specific interrupt

Figure 141. INT_GEN_6 Register Address: 0x71
76543210
ReservedINT_GEN_DSP3[2:0]ReservedINT_GEN_DSP4[2:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 119. Interrupt Generation 6 Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6-4INT_GEN_DSP3[2:0]RW0hDSP output interrupt 3 is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved
3ReservedRW0hReserved
2-0INT_GEN_DSP4[2:0]RW0hDSP output interrupt 4 is
0 = not used in the generation of interrupt

1 = used in the generation of INT1

2 = used in the generation of INT2

3 = used in the generation of INT3

4 = used in the generation of INT4

5-7 = Reserved

INT_IND_MODE (book=0x00 page=0x01 address=0x72) [reset=0h]

Configure how interrupts are reported.

Figure 142. INT_IND_MODE Register Address: 0x72
76543210
INT1_IND[1:0]INT2_IND[1:0]INT3_IND[1:0]INT4_IND[1:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 120. Interrupt Indication Mode Field Descriptions

BitFieldTypeResetDescription
7-6INT1_IND[1:0]RW0hInterrupt 1 pin will indicate an interrupt as
0 = one active high pulse of duration 2 ms

1 = multiple active high pulses of duration 2 ms with period 4 ms until INT_STICKY_1 and INT_STICKY_2 are read to be cleared.

2 = active high until INT_STICKY_1 and INT_STICKY_2 are read to be cleared.

2 = active high based instantaneous interrupt value
5-4INT2_IND[1:0]RW0hInterrupt 2 pin will indicate an interrupt as
0 = one active high pulse of duration 2 ms

1 = multiple active high pulses of duration 2 ms with period 4 ms until INT_STICKY_1 and INT_STICKY_2 are read to be cleared.

2 = active high until INT_STICKY_1 and INT_STICKY_2 are read to be cleared.

2 = active high based instantaneous interrupt value
3-2INT3_IND[1:0]RW0hInterrupt 3 pin will indicate an interrupt as
0 = one active high pulse of duration 2 ms

1 = multiple active high pulses of duration 2 ms with period 4 ms until INT_STICKY_1 and INT_STICKY_2 are read to be cleared.

2 = active high until INT_STICKY_1 and INT_STICKY_2 are read to be cleared.

2 = active high based instantaneous interrupt value
1-0INT4_IND[1:0]RW0hInterrupt 4 pin will indicate an interrupt as
0 = one active high pulse of duration 2 ms

1 = multiple active high pulses of duration 2 ms with period 4 ms until INT_STICKY_1 and INT_STICKY_2 are read to be cleared.

2 = active high until INT_STICKY_1 and INT_STICKY_2 are read to be cleared.

2 = active high based instantaneous interrupt value

MAIN_CLK_PIN (book=0x00 page=0x01 address=0x73) [reset=Dh]

Configures the main clock input source.

Figure 143. MAIN_CLK_PIN Register Address: 0x73
76543210
ReservedMAIN_CLK_DIN[3:0]
RW-0hRW-Dh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 121. Main Clock Source Field Descriptions

BitFieldTypeResetDescription
7-4ReservedRW0hReserved
3-0MAIN_CLK_DIN[3:0]RWDhNDIV_MUX_CLKIN input is from
0 = GPIO1

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6

6 = GPIO7

7 = GPIO8

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2 (Preferred pin usage)

14 = GPI3

15 = PLL_CLK generated on-cchip

PLL_CLK_PIN (book=0x00 page=0x01 address=0x74) [reset=Dh]

Configures the PLL clock input source.

Figure 144. PLL_CLK_PIN Register Address: 0x74
76543210
ReservedPLL_CLK_DIN[3:0]
RW-0hRW-Dh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 122. PLL Clock Source Field Descriptions

BitFieldTypeResetDescription
7-4ReservedRW0hReserved
3-0PLL_CLK_DIN[3:0]RWDhPLL_CLKIN input is from
0 = GPIO1

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6

6 = GPIO7

7 = GPIO8

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2 (Preferred pin usage)

14 = GPI3

15 = from internal oscillator

CLKOUT_MUX (book=0x00 page=0x01 address=0x75) [reset=Dh]

Configures the CDIV_CLKIN clock input source.

Figure 145. CLKOUT_MUX Register Address: 0x75
76543210
ReservedCLKOUT_DIN[4:0]
RW-0hRW-Dh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 123. CDIV_CLKIN Clock Source Field Descriptions

BitFieldTypeResetDescription
7-5ReservedRW0hReserved
4-0CLKOUT_DIN[4:0]RWDhCDIV_CLKIN input is from
0 = GPIO1

1 = GPIO2

2 = GPIO3

3 = GPIO4

4 = GPIO5

5 = GPIO6

6 = GPIO7

7 = GPIO8

8 = GPIO9

9 = GPIO10

10-11 = Reserved

12 = GPI1

13 = GPI2 (Preferred pin usage)

14 = GPI3

15 = PLL_CLK

16 = DAC_MOD_CLK

17 = ADC_MOD_CLK

18 = NDIV_CLK

19-31 = Reserved

CLKOUT_CDIV_RATIO (book=0x00 page=0x01 address=0x76) [reset=1h]

Configure the CDIV ratio and power.

Figure 146. CLKOUT_CDIV_RATIO Register Address: 0x76
76543210
CDIV_PWRCDIV_RTO[6:0]
RW-0hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 124. CLKOUT CDIV Ratio Field Descriptions

BitFieldTypeResetDescription
7CDIV_PWRRW0hThe CDIV divider is
0 = powered down

1 = powered up
6-0CDIV_RTO[6:0]RW1hThe CDIV ratio is
0 = 128

1 = 1

2 = 2

...

126 = 126

127 = 127

I2C_MISC (book=0x00 page=0x01 address=0x7C) [reset=0h]

Configures various I2C options

Figure 147. I2C_MISC Register Address: 0x7C
76543210
ReservedI2C_HDI2C_GCAEReserved
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 125. I2C Misc Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6I2C_HDRW0hI2C hang deteciton. Read to clear. Do not write this bit high. I2C hang is
0 = detected

1 = not detected
5I2C_GCAERW0hWhen enabled the part will respond to the configured I2C address as well as the general call I2C address. I2C general call address for multi-part loading is
0 = disabled

1 = enabled
4-0ReservedRW0hReserved

DEVICE_ID (book=0x00 page=0x01 address=0x7D) [reset=12h]

Used to indicate device

Figure 148. DEVICE_ID Register Address: 0x7D
76543210
DEV_ID[7:0]
R-12h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 126. Device ID Field Descriptions

BitFieldTypeResetDescription
7-0DEV_ID[7:0]R12h

PAGE (book=0x00 page=0x02 address=0x00) [reset=1h]

Selects the page for the next read or write.

Figure 149. PAGE Register Address: 0x00
76543210
PAGE[7:0]
RW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 127. Page Select Field Descriptions

BitFieldTypeResetDescription
7-0PAGE[7:0]RW1hSelects the Register Page for the next read or write command

RAMP_CTRL (book=0x00 page=0x02 address=0x06) [reset=0h]

Class-D Ramp Control

Figure 150. RAMP_CTRL Register Address: 0x06
76543210
ReservedRAMP_FREQ[1:0]ReservedRAMP_FREQMOD[1:0]
RW-0hRW-0hRW-0hRW-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 128. Class-D Ramp Control Field Descriptions

BitFieldTypeResetDescription
7-6ReservedRW0hReserved
5-4RAMP_FREQ[1:0]RW0hRampgen frequency is
0 = 384kHz, use this for Fs of 48ksps and its multiples

1 = 352.8kHz, Use this for Fs of 44.1ksps and its multiples

2 = Reserved
3-2ReservedRW0hReserved
1-0RAMP_FREQMOD[1:0]RW0hWhen SSM is enabled the ramp is modulated by
0 = Reserved

1 = +-5 %

2 = +-10 %

3 = Reserved

PROTECTION_CFG (book=0x00 page=0x02 address=0x09) [reset=3h]

Configures the Devices Protection Blocks

Figure 151. PROTECTION_CFG Register Address: 0x09
76543210
ReservedReservedReservedReservedReservedOT_RTReservedReserved
RW-0hRW-0hRW-0hRW-0hRW-0hRW-0hRW-1hRW-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 129. Configures the Devices Protection Blocks Field Descriptions

BitFieldTypeResetDescription
7ReservedRW0hReserved
6ReservedRW0hReserved
5ReservedRW0hReserved
4ReservedRW0hReserved
3ReservedRW0hReserved
2OT_RTRW0hDie over-temperature retry is
0 = Enabled

1 = Disabled
1ReservedRW1hReserved
0ReservedRW1hReserved