ZHCSFP7A November   2016  – February 2017 TAS2557

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. 说明(续)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  I2C Timing Requirements
    7. 8.7  SPI Timing Requirements
    8. 8.8  I2S/LJF/RJF Timing in Master Mode
    9. 8.9  I2S/LJF/RJF Timing in Slave Mode
    10. 8.10 DSP Timing in Master Mode
    11. 8.11 DSP Timing in Slave Mode
    12. 8.12 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  General I2C Operation
      2. 10.3.2  Single-Byte and Multiple-Byte Transfers
      3. 10.3.3  Single-Byte Write
      4. 10.3.4  Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 10.3.5  Single-Byte Read
      6. 10.3.6  Multiple-Byte Read
      7. 10.3.7  General SPI Operation
      8. 10.3.8  Class-D Edge Rate Control
      9. 10.3.9  IV Sense
      10. 10.3.10 Battery Tracking AGC
      11. 10.3.11 Boost Control
        1. 10.3.11.1 Boost Mode
        2. 10.3.11.2 Configurable Boost Current Limit (ILIM)
      12. 10.3.12 Thermal Fold-back
      13. 10.3.13 Fault Protection
        1. 10.3.13.1 Speaker Over-Current
        2. 10.3.13.2 Analog Under-Voltage
        3. 10.3.13.3 Die Over-Temperature
        4. 10.3.13.4 Clocking Faults
      14. 10.3.14 Brownout
      15. 10.3.15 Spread Spectrum vs Synchronized
      16. 10.3.16 IRQs and Flags
      17. 10.3.17 Software Reset
      18. 10.3.18 PurePath Console 3 Software TAS2557 Application
    4. 10.4 Device Functional Modes
      1. 10.4.1 Audio Digital I/O Interface
        1. 10.4.1.1 I2S Mode
        2. 10.4.1.2 DSP Mode
        3. 10.4.1.3 Right-Justified Mode (RJF)
        4. 10.4.1.4 Left-Justified Mode (LJF)
      2. 10.4.2 Mono PCM Mode
      3. 10.4.3 Stereo Application Example - TDM Mode
    5. 10.5 Operational Modes
      1. 10.5.1 Hardware Shutdown
      2. 10.5.2 Software Shutdown
      3. 10.5.3 Low Power Sleep
      4. 10.5.4 Software Reset
      5. 10.5.5 Device Processing Modes
        1. 10.5.5.1 Mode 1 - PCM input playback only
        2. 10.5.5.2 Mode 2 - PCM input playback + PCM IVsense output
        3. 10.5.5.3 Mode 3 - Smart Amp Mode
    6. 10.6 Programming
      1. 10.6.1 Code Loading and CRC check
      2. 10.6.2 Device Power Up and Unmute Sequence
      3. 10.6.3 Device Mute and Power Down Sequence
  11. 11Applications and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Detailed Design Procedure
          1. 11.2.1.1.1 Mono/Stereo Configuration
          2. 11.2.1.1.2 Boost Converter Passive Devices
          3. 11.2.1.1.3 EMI Passive Devices
          4. 11.2.1.1.4 Miscellaneous Passive Devices
      2. 11.2.2 Application Performance Plots
    3. 11.3 Initialization Set Up
  12. 12Power Supply Recommendations
    1. 12.1 Power Supplies
    2. 12.2 Power Supply Sequencing
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Register Map
    1. 14.1 Register Map Summary
      1. 14.1.1 Register Summary Table Book=0x00 Page=0x00
      2. 14.1.2 Register Summary Table Book=0x00 Page=0x01
      3. 14.1.3 Register Summary Table Book=0x00 Page=0x02
    2. 14.2 Register Maps
      1. 14.2.1   PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
      2. 14.2.2   RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
      3. 14.2.3   POWER_1 (book=0x00 page=0x00 address=0x04) [reset=0h]
      4. 14.2.4   POWER_2 (book=0x00 page=0x00 address=0x05) [reset=0h]
      5. 14.2.5   SPK_GAIN_EDGE (book=0x00 page=0x00 address=0x06) [reset=0h]
      6. 14.2.6   MUTE (book=0x00 page=0x00 address=0x07) [reset=0h]
      7. 14.2.7   SNS_CTRL (book=0x00 page=0x00 address=0x08) [reset=0h]
      8. 14.2.8   BOOST_CTRL_1 (book=0x00 page=0x00 address=0x09) [reset=0h]
      9. 14.2.9   SAR_CTRL_2 (book=0x00 page=0x00 address=0x14) [reset=32h]
      10. 14.2.10  SAR_CTRL_3 (book=0x00 page=0x00 address=0x15) [reset=4h]
      11. 14.2.11  SAR_VBAT_MSB (book=0x00 page=0x00 address=0x16) [reset=0h]
      12. 14.2.12  SAR_VBAT_LSB (book=0x00 page=0x00 address=0x17) [reset=0h]
      13. 14.2.13  SAR_VBST_MSB (book=0x00 page=0x00 address=0x18) [reset=0h]
      14. 14.2.14  SAR_VBST_LSB (book=0x00 page=0x00 address=0x19) [reset=0h]
      15. 14.2.15  SAR_TMP1_MSB (book=0x00 page=0x00 address=0x1A) [reset=0h]
      16. 14.2.16  SAR_TMP1_LSB (book=0x00 page=0x00 address=0x1B) [reset=0h]
      17. 14.2.17  SAR_TMP2_MSB (book=0x00 page=0x00 address=0x1C) [reset=0h]
      18. 14.2.18  SAR_TMP2_LSB (book=0x00 page=0x00 address=0x1D) [reset=0h]
      19. 14.2.19  CRC_CHECKSUM (book=0x00 page=0x00 address=0x20) [reset=0h]
      20. 14.2.20  CRC_RESET (book=0x00 page=0x00 address=0x21) [reset=0h]
      21. 14.2.21  DSP_CTRL (book=0x00 page=0x00 address=0x22) [reset=1h]
      22. 14.2.22  SSM_CTRL (book=0x00 page=0x00 address=0x28) [reset=0h]
      23. 14.2.23  ASI_CTRL_1 (book=0x00 page=0x00 address=0x2A) [reset=0h]
      24. 14.2.24  BOOST_CTRL_2 (book=0x00 page=0x00 address=0x2B) [reset=3h]
      25. 14.2.25  CLOCK_CTRL_1 (book=0x00 page=0x00 address=0x2C) [reset=0h]
      26. 14.2.26  CLOCK_CTRL_2 (book=0x00 page=0x00 address=0x2D) [reset=17h]
      27. 14.2.27  CLOCK_CTRL_3 (book=0x00 page=0x00 address=0x2E) [reset=0h]
      28. 14.2.28  ASI_CTRL_2 (book=0x00 page=0x00 address=0x2F) [reset=0h]
      29. 14.2.29  CLOCK_CTRL_4 (book=0x00 page=0x00 address=0x32) [reset=0h]
      30. 14.2.30  DEBUG_1 (book=0x00 page=0x00 address=0x35) [reset=0h]
      31. 14.2.31  POWER_STATUS (book=0x00 page=0x00 address=0x64) [reset=0h]
      32. 14.2.32  DSP_BOOT_STATUS (book=0x00 page=0x00 address=0x65) [reset=0h]
      33. 14.2.33  INT_DET_1 (book=0x00 page=0x00 address=0x68) [reset=0h]
      34. 14.2.34  INT_DET_2 (book=0x00 page=0x00 address=0x6C) [reset=0h]
      35. 14.2.35  LOW_POWER (book=0x00 page=0x00 address=0x79) [reset=0h]
      36. 14.2.36  BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
      37. 14.2.37  PAGE (book=0x00 page=0x01 address=0x00) [reset=1h]
      38. 14.2.38  ASI1_FORMAT (book=0x00 page=0x01 address=0x01) [reset=10h]
      39. 14.2.39  ASI1_OFFSET_1 (book=0x00 page=0x01 address=0x03) [reset=0h]
      40. 14.2.40  ASI1_BUSKEEP (book=0x00 page=0x01 address=0x05) [reset=0h]
      41. 14.2.41  ASI1_BCLK (book=0x00 page=0x01 address=0x08) [reset=0h]
      42. 14.2.42  ASI1_WCLK (book=0x00 page=0x01 address=0x09) [reset=8h]
      43. 14.2.43  ASI1_DIN_DOUT (book=0x00 page=0x01 address=0x0C) [reset=0h]
      44. 14.2.44  ASI1_BDIV_CLK (book=0x00 page=0x01 address=0x0D) [reset=1h]
      45. 14.2.45  ASI1_BDIV_RATIO (book=0x00 page=0x01 address=0x0E) [reset=2h]
      46. 14.2.46  ASI1_WDIV_RATIO (book=0x00 page=0x01 address=0x0F) [reset=20h]
      47. 14.2.47  ASI1_CLK_OUT (book=0x00 page=0x01 address=0x10) [reset=0h]
      48. 14.2.48  ASI2_FORMAT (book=0x00 page=0x01 address=0x15) [reset=10h]
      49. 14.2.49  ASI2_OFFSET_1 (book=0x00 page=0x01 address=0x17) [reset=0h]
      50. 14.2.50  ASI2_BUSKEEP (book=0x00 page=0x01 address=0x19) [reset=0h]
      51. 14.2.51  ASI2_BCLK (book=0x00 page=0x01 address=0x1C) [reset=20h]
      52. 14.2.52  ASI2_WCLK (book=0x00 page=0x01 address=0x1D) [reset=28h]
      53. 14.2.53  ASI2_DIN_DOUT (book=0x00 page=0x01 address=0x20) [reset=38h]
      54. 14.2.54  ASI2_BDIV_CLK (book=0x00 page=0x01 address=0x21) [reset=1h]
      55. 14.2.55  ASI2_BDIV_RATIO (book=0x00 page=0x01 address=0x22) [reset=2h]
      56. 14.2.56  ASI2_WDIV_RATIO (book=0x00 page=0x01 address=0x23) [reset=20h]
      57. 14.2.57  ASI2_CLK_OUT (book=0x00 page=0x01 address=0x24) [reset=33h]
      58. 14.2.58  GPIO1_PIN (book=0x00 page=0x01 address=0x3D) [reset=1h]
      59. 14.2.59  GPIO2_PIN (book=0x00 page=0x01 address=0x3E) [reset=1h]
      60. 14.2.60  GPIO3_PIN (book=0x00 page=0x01 address=0x3F) [reset=10h]
      61. 14.2.61  GPIO4_PIN (book=0x00 page=0x01 address=0x40) [reset=7h]
      62. 14.2.62  GPIO5_PIN (book=0x00 page=0x01 address=0x41) [reset=0h]
      63. 14.2.63  GPIO6_PIN (book=0x00 page=0x01 address=0x42) [reset=0h]
      64. 14.2.64  GPIO7_PIN (book=0x00 page=0x01 address=0x43) [reset=0h]
      65. 14.2.65  GPIO8_PIN (book=0x00 page=0x01 address=0x44) [reset=0h]
      66. 14.2.66  GPIO9_PIN (book=0x00 page=0x01 address=0x45) [reset=0h]
      67. 14.2.67  GPIO10_PIN (book=0x00 page=0x01 address=0x46) [reset=0h]
      68. 14.2.68  GPI_PIN (book=0x00 page=0x01 address=0x4D) [reset=0h]
      69. 14.2.69  GPIO_HIZ_1 (book=0x00 page=0x01 address=0x4F) [reset=0h]
      70. 14.2.70  GPIO_HIZ_2 (book=0x00 page=0x01 address=0x50) [reset=0h]
      71. 14.2.71  GPIO_HIZ_3 (book=0x00 page=0x01 address=0x51) [reset=0h]
      72. 14.2.72  GPIO_HIZ_4 (book=0x00 page=0x01 address=0x52) [reset=0h]
      73. 14.2.73  GPIO_HIZ_5 (book=0x00 page=0x01 address=0x53) [reset=0h]
      74. 14.2.74  BIT_BANG_OUT1 (book=0x00 page=0x01 address=0x58) [reset=0h]
      75. 14.2.75  BIT_BANG_OUT2 (book=0x00 page=0x01 address=0x59) [reset=0h]
      76. 14.2.76  BIT_BANG_IN1 (book=0x00 page=0x01 address=0x5A) [reset=0h]
      77. 14.2.77  BIT_BANG_IN2 (book=0x00 page=0x01 address=0x5B) [reset=0h]
      78. 14.2.78  BIT_BANG_IN3 (book=0x00 page=0x01 address=0x5C) [reset=0h]
      79. 14.2.79  ASIM_BUSKEEP (book=0x00 page=0x01 address=0x60) [reset=0h]
      80. 14.2.80  ASIM_MODE (book=0x00 page=0x01 address=0x61) [reset=8h]
      81. 14.2.81  ASIM_NUM_DEV (book=0x00 page=0x01 address=0x62) [reset=0h]
      82. 14.2.82  ASIM_FORMAT (book=0x00 page=0x01 address=0x63) [reset=10h]
      83. 14.2.83  ASIM_BDIV_CLK (book=0x00 page=0x01 address=0x64) [reset=1h]
      84. 14.2.84  ASIM_BDIV_RATIO (book=0x00 page=0x01 address=0x65) [reset=2h]
      85. 14.2.85  ASIM_WDIV_RATIO_1 (book=0x00 page=0x01 address=0x66) [reset=0h]
      86. 14.2.86  ASIM_WDIV_RATIO_2 (book=0x00 page=0x01 address=0x67) [reset=20h]
      87. 14.2.87  ASIM_BCLK (book=0x00 page=0x01 address=0x68) [reset=40h]
      88. 14.2.88  ASIM_WCLK (book=0x00 page=0x01 address=0x69) [reset=38h]
      89. 14.2.89  ASIM_DIN (book=0x00 page=0x01 address=0x6A) [reset=70h]
      90. 14.2.90  INT_GEN_1 (book=0x00 page=0x01 address=0x6C) [reset=0h]
      91. 14.2.91  INT_GEN_2 (book=0x00 page=0x01 address=0x6D) [reset=0h]
      92. 14.2.92  INT_GEN_3 (book=0x00 page=0x01 address=0x6E) [reset=0h]
      93. 14.2.93  INT_GEN_4 (book=0x00 page=0x01 address=0x6F) [reset=0h]
      94. 14.2.94  INT_GEN_5 (book=0x00 page=0x01 address=0x70) [reset=0h]
      95. 14.2.95  INT_GEN_6 (book=0x00 page=0x01 address=0x71) [reset=0h]
      96. 14.2.96  INT_IND_MODE (book=0x00 page=0x01 address=0x72) [reset=0h]
      97. 14.2.97  MAIN_CLK_PIN (book=0x00 page=0x01 address=0x73) [reset=Dh]
      98. 14.2.98  PLL_CLK_PIN (book=0x00 page=0x01 address=0x74) [reset=Dh]
      99. 14.2.99  CLKOUT_MUX (book=0x00 page=0x01 address=0x75) [reset=Dh]
      100. 14.2.100 CLKOUT_CDIV_RATIO (book=0x00 page=0x01 address=0x76) [reset=1h]
      101. 14.2.101 I2C_MISC (book=0x00 page=0x01 address=0x7C) [reset=0h]
      102. 14.2.102 DEVICE_ID (book=0x00 page=0x01 address=0x7D) [reset=12h]
      103. 14.2.103 PAGE (book=0x00 page=0x02 address=0x00) [reset=1h]
      104. 14.2.104 RAMP_CTRL (book=0x00 page=0x02 address=0x06) [reset=0h]
      105. 14.2.105 PROTECTION_CFG (book=0x00 page=0x02 address=0x09) [reset=3h]
  15. 15器件和文档支持
    1. 15.1 文档支持
    2. 15.2 社区资源
    3. 15.3 商标
    4. 15.4 静电放电警告
    5. 15.5 Glossary
  16. 16机械、封装和可订购信息
    1. 16.1 封装尺寸

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YZ|42
订购信息

Detailed Description

Overview

The TAS2557 device is a state-of-the-art Class-D audio amplifier which is a full system on a chip (SoC). The device features a ultra low-noise audio DAC and Class-D power amplifier which incorporates speaker voltage and current sensing feedback. An on-chip, low-latency DSP supports Texas Instruments' Smart Amp speaker protection algorithms to maximize loudness while maintaining safe speaker conditions. A smart integrated multi-level Class-H boost converter maximizes system efficiency at all times by tracking the required output voltage. The TAS2557 drives up to 3.8 W from a 4.2-V supply into an 8-Ω speaker with 1% THD, or up to up 5.7 W into a 4-Ω speaker with 1% THD.

The TAS2557 , with final processed digital output, can also be used to increase loudness and clarity in both Noise Canceling / Echo Cancelling speaker phone applications as well as for music or other sound applications. The TAS2557 accepts input audio data rates from 8 kHz to 96 kHz using ROM modes to fully support both speakerphone and music applications. When speaker protection system is running the maximum sampling rate is limited to 48 kHz.

The multi-level Class-H boost converter generates the Class-D amplifier supply rail. When the audio signal requires a output power below VBAT, the boost improves system efficiency by deactivating and connecting VBAT directly to the Class-D amplifier supply. When higher audio output power is required, the boost quickly activates and provides a much louder and clearer signal than can be achieved in any standard amplifier speaker system design approach. A boost inductor of 1uH can be used with a slight increase in boost ripple.

On-chip brownout detection system shutdown down audio at the user configurable threshold to avoid undesired system reset. In addition, an AGC can be selected to minimize clipping events when a lower power supply voltage is provided to the Class-D speaker driver. When this supply voltage drops below the proper level then under-voltage protection will be tripped. All protection statuses are available via register reads.

The Class-D output switching frequency is synchronous with the digital input audio sample rate to avoid left and right PWM frequency differences from beating in stereo applications. PWM Edge rate control and Spread Spectrum features are available if further EMI reduction is desired in the user’s system.

The interrupt request pin (IRQ) indicates a device error condition. The interrupt flag condition or conditions are selectable via I2C and include: thermal overload, Class-D over-current, VBAT level low, VBOOST level low, and PLL out-of-lock conditions. The IRQ signal is active-high for an interrupt request and low during normal operation. This behavior can be changed by a register setting to tri-state the pin during normal operation to allow the IRQ pin to be tied in parallel with other active-low interrupt request pins on other devices in the system.

Stereo configuration can be achieved with two TAS2557 devices by using the ADR0_SCLK and ADR1_MISO pins to set different I2C addresses in I2C mode or the SCL_SSZ chip enable pin in SPI mode. Refer to the General I2C Operation or General SPI Operation sections for more details.

Functional Block Diagram

TAS2557 fbd_2557.gif

Feature Description

General I2C Operation

The TAS2557 operates as an I2C slave over the IOVDD voltage range. It is adjustable to one of four I2C addresses. This allows multiple TAS2557 devices in a system to connect to the same I2C bus. The I2C pins are fail-safe. If the part is not powered or is in shutdown the I2C pins will not impact the I2C bus allowing it to remain functional.

To configure the TAS2557 for I2C operation set the SPI_SELECT pin to ground. The I2C address can then be set using pins ADR0_SCLK and ADR1_MSIO according to Table 1. The pins configure the two LSB bits of the following 7-bit binary address A6-A0 of 10011xx. This permits the I2C address of TAS2557 to be 0x4C(7-bit) through 0x4F(7-bit). For example, if both ADR0_SCLK and ADR1_MSIO are connected to ground the I2C address for the TAS2557 would be 0x4C(7-bit). This is equivalent to 0x98 (8-bit) for writing and 0x99 (8-bit) for reading.

Table 1. I2C Address Selection

ADR0_SCLK Pin ConnectionADR1_MSIO Pin ConnectionI2C Device Address
GND GND0x4C
IOVDDGND0x4D
GNDIOVDD0x4E
IOVDDIOVDD0x4F

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The corresponding pins on the TAS2557 for the two signals are SDA_MOSI and SCL_SSZ. The bus transfers data serially, one bit at a time. The address and data (8-bit) bytes are transferred most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 19 shows a typical sequence.

The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The device holds SDA low during the acknowledge clock period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bi-directional bus using a wired-AND connection.

Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Use pull-up resistors between 660 Ω and 4.7 kΩ. Do not allow the SDA and SCL voltages to exceed the device supply voltage, IOVDD.

TAS2557 i2c_seq_los492.gif Figure 19. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. Figure 19 shows a generic data transfer sequence.

Single-Byte and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for all registers. During multiple-byte read operations, the TAS2557 responds with data, a byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledges.

The TAS2557 supports sequential I2C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.

Single-Byte Write

As shown in Figure 20, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C device address and the read/write bit, the TAS2557 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the device internal memory address being accessed. After receiving the register byte, the device again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

TAS2557 sbw_trn_los492.gif Figure 20. Single-Byte Write Transfer

Multiple-Byte Write and Incremental Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TAS2557 as shown in Figure 21. After receiving each data byte, the device responds with an acknowledge bit.

TAS2557 mbw_trn_los492.gif Figure 21. Multiple-Byte Write Transfer

Single-Byte Read

As shown in Figure 22, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is set to a 0.

After receiving the TAS2557 address and the read/write bit, the device responds with an acknowledge bit. The master then sends the internal memory address byte, after which the device issues an acknowledge bit. The master device transmits another start condition followed by the TAS2557 address and the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the TAS2557 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.

TAS2557 sbr_trn_los492.gif Figure 22. Single-Byte Read Transfer

Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the TAS2557 to the master device as shown in Figure 23. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

TAS2557 mbr_trn_los492.gif Figure 23. Multiple-Byte Read Transfer

General SPI Operation

The TAS2557 operates as an SPI slave over the IOVDD voltage range.

Class-D Edge Rate Control

The edge rate of the Class-D output is controllable via I2C as shown in Table 2. This allows adjusting the switching edge rate of the Class-D amplifier, trading off efficiency for lower EMI. The default edge rate of 14ns passes EMI testing and is recommend but may be changed if required.

Table 2. Class-D Edge Rate Control

SPK_GAIN_EDGE[2:0] (EDGE_RATE)tR AND tF
(TYPICAL)
000Reserved
001Reserved
01029 ns
01125 ns
10014 ns (default)
10113 ns
11012 ns
11111 ns

IV Sense

The TAS2557 provides speaker voltage and current sense for real-time monitoring of loudspeaker behavior. The VSENSE_P and VSENSE_N pins should be connected after any ferrite bead filter (or directly to the SPK_P and SPK_N connections if no EMI filter is used). The V-Sense terminals are used to eliminate IR drop error due to packaging, PCB interconnect, and ferrite bead filter resistance. The V-sense terminals are also used to close the Class-D feedback loop post filter. This Post-Filter Feedback (PFFB) minimizes the THD introduced from the filter-beads used in the system. Any interconnect resistance or non-linearities after the V-Sense terminals connection point will not be corrected for. Therefore, it is advised to connect the sense connections as close to the load as possible.

TAS2557 vsns_connect.gif Figure 24. V-Sense Connections

The I-Sense can be configured for three ranges and shown in Table 3. This should be set appropriately based on the DC resistance of the speaker. I-Sense and V-Sense can additionally be powered down as shown in Table 4 and Table 5. When powered down, the device will return null samples for the powered down sense channels.

Table 3. I-Sense Current Range

SNS_CTRL[2:1] (ISNS_SCALE)Full Scale CurrentSpeaker Load Impedance
001.25 A (default)8 Ω
011.5 A6 Ω
101.75 A4 Ω
11ReservedReserved

Table 4. I-Sense Mute

MUTE[1] (MUTE_ISNS)Setting
0I-Sense is active (default)
1I-Sense channel is muted

Table 5. V-Sense Mute

MUTE[0] (MUTE_VSNS)Setting
0V-Sense is active (default)
1V-Sense channel is muted

Table 6. I-Sense Power Down

POWER_2[1] (PWR_ISNS)Setting
0I-Sense is active (default)
1I-Sense is powered down

Table 7. V-Sense Power Down

POWER_2[0] (PWR_VSNS)Setting
0V-Sense is active (default)
1V-Sense is powered down

Battery Tracking AGC

The TAS2557 monitors the battery voltage and audio signal to automatically decrease gain when the battery voltage is low and audio output power is high. This provides louder audio while preventing early shutdown at end-of-charge battery voltage levels. The battery tracking AGC starts to attenuate the signal once the voltage at the Class-D output exceeds VLIM for a given battery voltage (VBAT). If the Class-D output voltage is below the VLIM value, no attenuation occurs. If the Class-D output exceeds the VLIM value the AGC starts to attack the signal and reduce the gain until the output is reduced to VLIM. Once the signal returns below VLIM plus some hysteresis the gain reduction decays. The VLIM is constant above the user configurable inflection point. Below the inflection point the VLIM is reduced by a user configurable slope in relation to the battery voltage. The attack time, decay time, inflection point and VLIM/VBAT slope below the inflection point are user configurable. The parameters for the battery tracking AGC are part of the DSP core and can be set using the PurePath Console 3 Software TAS2557 Application software for the TAS2557 part under the Device Control Tab. Below a VBAT level of 2.9 V, the boost will turn on to ensure correct operation but results in increased current consumption. The device is functional until the set brownout level is reached and the device shuts down. The minimum brownout voltage is 2.7 V.

TAS2557 SpeakerGuard_las898.gif Figure 25. VLIM versus Supply Voltage (VBAT)

Boost Control

Boost Mode

The TAS2557 internal processing algorithm automatically enables the boost when needed. A look-ahead algorithm monitors the battery voltage and the digital audio stream. When the speaker output approaches the battery voltage the boost is enabled in-time to supply the required speaker output voltage. When the boost is no longer required it is disabled and bypassed to maximize efficiency. The boost can be configured in one of two modes. The first is low in-rush (Class-G) supporting only boost on-off and has the lowest in-rush current. The second is high-efficiency (Class-H) where the boost voltage level is adjusted to a value just above what is needed. This mode is more efficient but has a higher in-rush current to quickly transition the levels. This can be configured using Table 8.

TAS2557 boost_options.gif Figure 26. Boost Mode Signal Tracking Example

Table 8. Boost Mode

SPK_CTRL[4] (BST_MODE)Boost Mode
0Class-H - High efficiency
1Class-G - Low in-rush (default)

Configurable Boost Current Limit (ILIM)

The TAS2557 device has a configurable boost current limit (ILIM). The default current limit is 3 A but this limit may be set lower based on selection of passive components connected to the boost. The TAS2557 device supports 4 different boost limits.

Table 9. Current Limit Settings

BOOST_CTRL_2[1:0] (BST_ILM)BOOST CURRENT LIMIT (A)
001.5
012.0
102.5
113.0 (default)

Thermal Fold-back

The TAS2557 monitors the die temperature and prevents it from going over a set limit. When enabled, an internal controller will automatically adjust the signal path gain to prevent the die temperature from exceeding this limit. This allows instantaneous peak power to be delivered to the speaker while limiting the continuous power to prevent thermal shutdown. The configuration parameters for the thermal fold-back are part of the DSP core and can be set using the PurePath Console 3 Software TAS2557 Application software for the TAS2557 part under the Device Control Tab.

Fault Protection

The TAS2557 has several protection blocks to prevent damage. Use of these blocks including how to resume from a fault are presented in this section.

Speaker Over-Current

The TAS2557 has an integrated over-current protection that is enabled once the Class-D is powered up. Large currents in the range of 3-5 A on the Class-D output will trigger an over-current fault. Once the fault is detected, the TAS2557 disables the audio channel and powers down the Class-D amplifier. When an over-current event occurs, a status flag INT_OC is set. This register is sticky, and the bit remains high until the bit is read or the device is reset. The over-current event can also be used to generate an interrupt if required. Refer to IRQs and Flags section for more details. To re-enable the audio channel after a fault the Class-D, the device must be hardware or software reset and configuration must be re-loaded.

Analog Under-Voltage

The TAS2557 has integrated undervoltage protection on the analog power supply lines AVDD and VBAT. The undervoltage limit fault is triggered when AVDD is less than 1.5 V or when VBAT is less than 2.4 V. Once the fault is detected the TAS2557 will disable the audio channel and power down the Class-D amplifier. When an under-voltage event occurs, a status flag INT_UV is set. This register is sticky and the bit will remain high until the bit is read or the device is reset. The undervoltage event can also be used to generate an interrupt if required. Refer to IRQs and Flags section for more details. To re-enable the audio channel after a fault, the Class-D must be re-enabled by setting PWR_SPK high. All other configurations are preserved and the audio channel will power up with the last configured settings.

Die Over-Temperature

The TAS2557 has an integrated over-temperature protection that is enabled once the Class-D is powered up. If the device internal junction temperature exceeds the safe operating region it will trigger the over-temperature fault. Once the fault is detected the TAS2557 disables the audio channel and powers down the Class-D amplifier. The device waits until the user reads the over-temperature flag INT_OT to re-enable the Class-D amplifier if the junction temperature returns into a safe operating region. When an over-temperature event occurs, a status flag INT_OT is set. This register is sticky and the bit will remain high for as long as it is not read, or the device is not reset. The over-temperature event can also be used to generate an interrupt if required. Refer to IRQs and Flags section for more details. The over-temperature automatic re-enable can be disabled by setting OT_RT signal. If the automatic re-enable is disabled, the Class-D must be re-enabled by setting PWR_SPK high after the over-temperature fault. All other configurations are preserved and the audio channel will power up with the last configured settings.

Clocking Faults

The TAS2557 has two clock error detection blocks. The first is on the Audio Serial Interfaces (ASI). If a clock error is detected on the ASI interfaces, audio artifacts can occur at the Class-D output. When enabled, the ASI clock error detection can mute the device and shutdown the Class-D and DSP core. The clock error detection block is enabled by setting register signal CE1_EN. The ASI1 or ASI2 clocks can be routed to the block for detection using register CE1_IC. Additionally, the clock error can be routed to an interrupt pin, and the sticky bit INT_CLK1 indicates whether the clock error occurred. The second clock error detection block can monitor the DAC, ADC, and PLL clocks. When a clock error is detected, the output is soft-muted and the Class-D powered down. This clock error detection is enabled using bit signal CE2_EN and can be routed to the interrupt pin. It is indicated in the sticky bit INT_CLK2.

When a clocking error occurs, the following sequence should be performed to restart the device.

  • Clear the clock error interrupts by reading the sticky flags at registers INT_STICKY_2 and INT_STICKY_2
  • Clear the power error signal PWR_ERR in register POWER_1

Brownout

The TAS2557 has an integrated brownout system to shutdown the device when the battery voltage drops to an insufficient level. This user configurable level can be set under Device Control in the PurePath Console 3 Software TAS2557 Application. When brownout event occurs a status flag INT_BO is set. This register is sticky, and the bit remains high until the bit is read or the device is reset. The brownout event can also be used to generate an interrupt if required. Refer to IRQs and Flags section for more details. Once the battery voltage drops below the defined threshold, the following actions occur.

  • The audio playback is muted in a soft-stepping manner
  • DSP, clock dividers, and analog blocks are powered down
  • Sticky bit INT_BO is set

Once the host is aware of the brownout, it should set PWR_ERR register signal low to put the TAS2557 device in software shutdown and enters low power mode. Once the battery supply is stable above the defined brownout threshold the host can re-enable the device using the power control registers POWER_1 and POWER_2.

Spread Spectrum vs Synchronized

The Class-D switching frequency can be selected to work in two different modes of operations. This configuration needs to be done before powering up the audio channel. The first is a synchronized mode where the Class-D frequency is synchronized to the audio input sample rate. This is the default mode of operation and should be used in stereo applications to avoid inter-modulation beating of the Class-D frequency from multiple chips. The Class-D switching frequency in this mode can be configured as 384 kHz or 352.8 kHz. The 384 kHz frequency is the default mode of operation and can be used for input signals running on clock rates of 48 kHz or its sub-multiples. For input signals running on clock rate of 44.1 kHz and its sub-multiples, the switching frequency can be selected as 352.8 kHz using Table 10.

The second mode uses the internal oscillator to generate the ramp clock. This is enabled using Table 11. This mode is generally used with Table 12 enabled for spread-spectrum. Spread-specturm is used to reduce wideband spectral content improving EMI emissions radiated by the speaker. In this mode, the Class-D switching frequency can varies ±5% or ±10% as set by Table 13 about the set frequency Table 10.

The configuration for this block should be set using the PurePath Console 3 Software TAS2557 Application software for the TAS2557 part under the Device Control Tab.

Table 10. Ramp Clock Frequency

RAMP_CTRL[5:4] (RAMP_FREQ)Setting
00384 kHz (default)
01352.8 kHz
10Reserved
11Reserved

Table 11. Ramp Clock Source

RAMP_DSP[7] (RAMP_SRC)Setting
0Sync Mode - ramp generated from digital audio clock (default)
1Fixed Frequency Mode(FFM) - ramp generated from internal oscillator

Table 12. Ramp Clock SSM

SSM_CTRL[0] (SSM_EN)Setting
0SSM mode is disabled
1SSM mode is enabled(1)
Ramp clock source must be from internal oscillator

Table 13. Ramp SSM Mode

RAMP_CTRL[1:0] (RAMP_FREQMOD)Setting
00Reserved
01SSM mode enabled with ramp frequency modulated for ±5 % (default)
10SSM mode enabled with ramp frequency modulated for ±10 %
11Reserved

IRQs and Flags

Internal device flags such as over-current, under-voltage, etc. can be routed as interrupts. The device has 4 interrupts (INT1 - INT4) that can be routed to any of the 10 GPIO pins. If more than one flag is assigned to the same interrupt, the interrupt output is the logical OR-ing of all flags. If multiple flag's are assigned to the same interrupt, the host should then query the flags sticky register to determine which event triggered the interrupt. The 10 GPIO pins can be configured for any interrupt and can be configured using GPIOx_PIN registers.

Table 14. Interrupt Registers

Flag DescriptionSticky Register Bit Register to Route Flag to Interrupt
Over-CurrentINT_DET_1[7] (INT_OC)INT_GEN_1[6:4] (INT_GEN_OC)
Under-Voltage INT_DET_1[6] (INT_UV)INT_GEN_1[2:0] (INT_GEN_OV)
Over-TemperatureINT_DET_1[4] (INT_OT)INT_GEN_2[2:0] (INT_GEN_OT)
BrownoutINT_DET_1[3] (INT_BO)INT_GEN_3[6:4] (INT_GEN_BO)
Clock LostINT_DET_1[2] (INT_CL)INT_GEN_4[2:0] (INT_GEN_CL)
SAR CompleteINT_DET_1[1] (INT_SC)INT_GEN_4[6:4] (INT_GEN_SC)
Clock Error 1INT_DET_2[3] (INT_CE1)INT_GEN_2[6:4] (INT_GEN_CE1)
Clock Error 2INT_DET_2[2] (INT_CE2)INT_GEN_3[3:0] (INT_GEN_CE2)

For example, to route the brownout and under-voltage flags to GPIO5 (Pin IRQ_GPIO5) the following register settings would be used. The brownout flag would be routed to INT1 by setting INT_GEN_BO=001, and under-voltage flag would also be routed to INT1 by setting INT_GEN_OV=001. The pin IRQ_GPIO4 would be set to use INT1 by setting GP4_OUT=0x07

Software Reset

The TAS2557 internal logic must be initialized to a known condition for proper device function by doing a software reset. Performing software reset after a hardware reset is mandatory for reliable device boot up. To perform software reset, write high register signal RESET. After reset, all registers are initialized with default values as listed in the Register Map, and no register read/write should be performed within 100us.

PurePath™ Console 3 Software TAS2557 Application

The TAS2557 contains an integrated DSP engine for speaker protection. PurePath™ Console 3 (PPC3) is the software tool used to setup most device configurations and tuning features. Once the software is downloaded and installed from the TI website, the TAS2557 application can be download from within the software. This datasheet refers to options that can be configured using the PPC3 software tool.

PurePath Console 3 is an intuitive graphical user interface (GUI) for characterizing and tuning speakers. Step-by-step wizards guide developers through speaker characterization and system calibration. After characterization, the PPC3 provides visual representations of speaker capabilities and frequency response. Easy to use, real-time tuning information supported via mouse-over and complete process walk-throughs. PPC3 has full access to device registers and is the simplest way to modify device settings, EVM and learning board configuration. From speaker assessment to production, PPC3 is your simple, single development tool.

Device Functional Modes

Audio Digital I/O Interface

Audio data is transferred between the host processor and the TAS2557 via the digital audio serial interface (ASI), or audio bus. The ASI buses (ASI1 and ASI2) can be configured for left or right-justified, I2S, DSP, or TDM modes of operation. Standard telephony PCM interfaces are supported within the TDM mode.. These modes are all MSB-first, with data width programmable to 16, 20, 24, or 32 bits. In addition, the WCLK and BCLK can be independently configured in either master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies.

Table 15. ASI PCM Mode

ASI1_FORMAT[4:2] (ASI1_MODE)ASI2_FORMAT[4:2] (ASI2_MODE)ASI Function Mode
000000I2S Mode (default)
001001DSP Mode
010010Right-Justified Mode (RJF)
011011Left-Justified Mode (LJF)
100100 Mono PCM Mode

Table 16. ASI PCM Input Word Length

ASI1_FORMAT[1:0] (ASI1_LENGTH)ASI2_FORMAT[1:0] (ASI2_LENGTH)Word Length
000016 bits
010120 bits
101024 bits (default)
111132 bits

The bit clock (BCLK) is used to clock in and clock out the digital audio data across the serial bus. This signal can be programmed to generate variable clock pulses by controlling the BCLK multiply-divide factor in Registers 0x08 through 0x10. The number of BCLK pulses in a frame may need adjustment to accommodate various word-lengths as well as to support the case when multiple TAS2557 devices may share the same audio bus.

The TAS2557 also includes a feature to offset the position of start of data transfer with respect to the wordclock (WCLK). This offset is specified in number of BCLKs. This can be used in cases where there is a non-zero bit-clock delay from WCLK edge or to support TDM modes of operation. The TAS2557 can place the DOUT line into a Hi-Z (tri-state) condition during all BCLKs when valid data is not being sent. TDM mode is useable with I2S, LJF, RJF, and DSP interface modes and is required for stereo applications when more than one TAS2557 part is used. The TAS2557 also has a bus keeper circuit that can be enabled in tri-sate mode. The bus-keeper is a weak internal latch that will hold the data line state without the need for external pull-up or pull-down resistors while signal lines are in the Hi-Z or non-driven state.

Table 17. ASI OFFSET1

ASI1_OFFSET_1 (ASI_OFFSET1)ASI2_OFFSET_1 (ASI2_OFFSET1)BCLKs from WCLK edge for data channel
0x000x000 (default)
0x010x011
0x020x022
.........
0xFF0xFF255

Table 18. ASI Tri-state

ASI1_FORMAT[0] (ASI1_TRISTATE)ASI2_FORMAT[0] (ASI2_TRISTATE)Tri-state DOUT for extra BCLK cycles after frame is complete
00disabled (default)
11enabled

Table 19. ASI Bus-keeper

ASI1_BUSKEEP[7] (ASI1_BKP)ASI2_BUSKEEP[7] (ASI2_BKP)Tri-state DOUT for extra BCLK cycles after frame is complete
00disabled (default)
11enabled

Additional configuration options for the ASI1 and ASI2 interface can be found in the Register Map. It is recommended to use the PurePath Console 3 Software TAS2557 Application software for TAS2557 to configure the ASI interfaces.

I2S Mode

In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

TAS2557 t_dia_los585.gif Figure 27. Timing Diagram for I2S Mode
TAS2557 t_dis_offset_los585.gif Figure 28. Timing Diagram for I2S Mode with ASI_OFFSET1 = 2
TAS2557 t_dis_inv_los585.gif Figure 29. Timing Diagram for I2S Mode with ASI_OFFSET1 = 0 and Inverted Bit Clock

For I2S mode, the number of bit-clocks per channel should be greater than or equal to the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

DSP Mode

In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.

TAS2557 t_dsp_los585.gif Figure 30. Timing Diagram for DSP Mode
TAS2557 t_dsp_offset_los585.gif Figure 31. Timing Diagram for DSP Mode with ASI_OFFSET1=1
TAS2557 t_dsp_inv_los585.gif Figure 32. Timing Diagram for DSP Mode with ASI_OFFSET1=0 and Inverted Bit Clock

For DSP mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

Right-Justified Mode (RJF)

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

TAS2557 t_rt_jus_los585.gif Figure 33. Timing Diagram for Right-Justified Mode

For right-justified mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data.

Left-Justified Mode (LJF)

In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock.

TAS2557 t_lft_jus_los585.gif Figure 34. Timing Diagram for Left-Justified Mode
TAS2557 t_lft_offset_los585.gif Figure 35. Timing Diagram for Light-Left Mode with ASI_OFFSET1 = 1
TAS2557 t_lft_inv_los585.gif Figure 36. Timing Diagram for Left-Justified Mode with ASI_OFFSET1 = 0 and Inverted Bit Clock

For left-justified mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of the data. Also, the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

Mono PCM Mode

In mono PCM mode, the rising edge of the word clock starts the data transfer of the single channel of data. Each data bit is valid on the falling edge of the bit clock.

TAS2557 f3262_mono_pcm.gif Figure 37. Timing Diagram for Mono PCM Mode
TAS2557 f3262_mono_pcm_2.gif Figure 38. Timing Diagram for Mono PCM Mode with ASI_OFFSET1=2
TAS2557 f3262_mono_pcm_3.gif Figure 39. Timing Diagram for Mono PCM Mode with ASI_OFFSET1=2 and Bit Clock Inverted

For mono PCM mode, the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

Stereo Application Example - TDM Mode

Time-division multiplexing (TDM) is required for two or more devices to share a common DIN connection and a common DOUT connection. Using TDM mode, all devices transmit their DOUT data in user-specified sub-frames within one WCLK period. When one device transmits its DOUT information, the other devices place their DOUT terminals in a high impedance tri-state mode. The host processor can operate in I2S mode while the TAS2557 is running in I2S TDM mode to support sharing of the same DOUT line.

TDM mode is useable with I2S, LJF, RJF, and DSP interface modes. Refer to the respective sections for a description of how to set the TAS2557 into those modes.

TAS2557 t_dis_offset_los585.gif Figure 40. Timing Diagram for I2S in TDM Mode with ASI_OFFSET1=2

For TDM mode, the number of bit-clocks per frame should be less than the programmed word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least the programmed word-length of the data.

Operational Modes

Hardware Shutdown

The device enters hardware shutdown mode if the RESETZ pin is asserted low. In hardware shutdown mode, the device consumes the minimum quiescent current from VDD and VBAT supplies. All registers loose state in this mode and I2C communication is disabled.

If RESETZ is asserted low while audio is playing, the device immediately stops operation and enters hardware shutdown mode. This may result in pops or clicks. It is recommend to first enter software shutdown before entering hardware shutdown.

When RESETZ is released, the device will enter software shutdown. A power up sequence such as with the appropriate mode selected should be executed to exit shutdown in the desired mode of operation.

Software Shutdown

Software shutdown mode powers down all analog blocks required to playback audio, but does not cause the device to lose register state. Software shutdown is enabled by following Device Power Up and Unmute Sequence.

Low Power Sleep

The device has a low power sleep (Table 20) mode option to reduce the power consumption on analog supply VBAT. In order to use this operating mode, the VBAT and AVDD supply should remain powered up when in this mode. This mode disables the Power-on Reset connected to the VBAT supply reducing current consumption.

Table 20. Low Power Sleep

LOW_PWR[7] (VBAT_POR)Low Power Sleep Mode
0Disabled (default)
1Enabled - VBAT POR shutdown

Software Reset

The TAS2557 internal logic must be initialized to a known condition for proper device function by doing a software reset. Performing software reset after a hardware reset is mandatory for reliable device boot up. A software reset can be accomplished by asserting RESET bit in Table 21, which is self clearing. This will restore all registers to their default values. After software reset is performed, no register read/write should be performed within 100us while initialization sequence occurs.

Table 21. Software Reset

RESET[0] (RESET)Action
0Don't reset (default)
1Reset(Self clearing)

Device Processing Modes

The TAS2557 DSP can be initialized into one of three modes. The advanced processing features in these modes, such as battery guard, thermal fold-back, brownout, and boost are configured using PurePath Console 3 Software TAS2557 Application

Table 22. Device Power Mode

BOOT_MODE[3:0] (DSP_MODE)Operating Mode
0000Reserved
0001Mode 1 - PCM input playback only (default)
0010Mode 2 - PCM input playback + PCM IVsense output
0011Mode 3 - Smart Amp Mode

Mode 1 - PCM input playback only

ROM mode 1 provides the quickest initialization for the TAS2557 power up and is the lowest power mode. This mode can be used to play a known power up audio sequence before the rest of the audio system software is loaded. The mode provides fault protection, brownout protection, volume control, and Class-H controller. The EQ and Battery Guard can be enabled wth minimal additional configuration. The speaker protection algorithm is not running in this mode and the I/V sense ADCs are powered down to minimize power consumption. The PLL can be disabled for even lower power consumption if the MCLK supplied is at least 12.288MHz for any fs which is multiple or sub-multiple of 48kHz, or 11.2896 MHz for Fs of 44.1kHz. This mode should be used to characterize the electrical performance on the TAS2557 without any influence from the protection algorithm present in other modes.

TAS2557 Rom-Mode1.gif Figure 41. ROM Mode 1 Processing Block Diagram

Mode 2 - PCM input playback + PCM IVsense output

ROM mode 2 is similar to ROM mode 1 except the I/V sense ADCs are powered up and the data is routed back on the L/R return channels of the ASI port. This mode can be used to return the I/V data to the host and perform alternate computations on the speaker I/V measurements.

TAS2557 Rom_Mode2.gif Figure 42. ROM Mode 2 Processing Block Diagram

Mode 3 - Smart Amp Mode

Smart Amp Mode is used to run the TI Smart Amp algorithm on the built in DSP. This mode involves loading larger output files generated from the PurePath Console 3 Software TAS2557 Application. The generated files contain the speaker models, equalization, and additional configuration parameters in a format to load over the I2C or SPI interface. TI's Smart Amp provides thermal and excursion protection using initial speaker models and the current and voltage feedback. This allows TAS2557 to determine exact coil temperature and update the initial model due to variations in speaker and ambient conditions. More information about this mode can be found in the PurePath Console 3 Software TAS2557 Application.

Programming

While the below scripts are provided as configuration examples, it is recommended to use PurePath Console 3 Software TAS2557 Application software to generate the device configuration files. This software contains configuration checks to ensure proper settings are used in the device for various cases and loaded the needed fixed-function DSP patches.

Code Loading and CRC check

The TI Smart Amp software is loaded into program ram (PRAM) through writes to mapped memory registers. The encrypted binary software is downloaded and decoded on chip. Therefore read-back of the PRAM is disabled. However an 8-bit CRC checksum is provided to the customer to verify the code was correctly written to PRAM error-free. Once the software download is complete, the calculated 8-bit CRC checksum can be read from register CRC_CHECKSUM. If this value matches the checksum supplied with the program, the load to PRAM was successful. If new PRAM code is loaded the TAS2557 device should first be software or hardware reset to clear the CRC checksum register so that a proper checksum from the new code to be loaded.

The following is an example script used to load the DSP software and verify the CRC checksum.

##############################################################################################This script is a demo for downloading the PRAM code and checking CRC checksumi i2cstd#mclk expected is 24.576 MHz#configuring device registers for 8 ohm speaker load########################### DEVICE INIT SEQ START##############################################w 98 00 00 #Page-0w 98 7f 00 #Book-0w 98 01 01 #Software reset d 1 # wait 100us time for OTP-One Time Programmable memory values to be transferred to device ##### INIT SECTION STARTw 98 7f 64 # book 100w 98 46 01 # IRAM bootw 98 7f 00 # book 0##### INIT SECTION END##### DSP PROG SETTING STARTw 98 7f 64w 98 00 01#add writes for download to PRAM herew 98 00 00w 98 7f 00##### DSP PROG SETTING END########################### DEVICE INIT SEQ END ###############################################r 98 20 1 # reading the CRC checksum for the PRAM download , if read = CRC checksum provided to customer => PRAM download success ################### CHANNEL POWER UP ####################################################w 98 05 A3 # Power up Analog Blocksw 98 04 B8 # Power up DSP and clock dividersw 98 07 00 # Unmute Analog Blocksw 98 7f 64 # switch to book100w 98 07 00 # Soft stepped unmute of audio playback################################################################################################# DSP coeff update START# d 1# DSP filter coefficient update if required##### DSP coeff update END############device powered up and running############################# CHANNEL POWER DOWN ####################################################w 98 07 01 # Soft stepped mute of audio playbackd 10 # wait for DSP to mute classD after soft step down of audio# instead of delay alternatively status flag B120_P15_R120_R121_R122_R123 polling can be done and wait till R122_D0 = '1'.w 98 7f 00 # switch to book0w 98 07 03 # Mute Analog Blocksw 98 04 20 # Power down DSP and clock dividers (except Ndivider)w 98 05 00 # Power down Analog Blocks w 98 00 00 # NOP w 98 04 00 # Power down Ndivider ##############################################################################################optional(ending the script in B0_P0)w 98 00 00 # page 0w 98 7f 00 # book 0#############################################################################################

Device Power Up and Unmute Sequence

The following code example provide the correct sequence to power up and unmute the device. The PurePath Console 3 Software TAS2557 Application software will create output files with these commands. The following is a example of powering up the part in DSP Mode 2 with proper sequencing.

Example script (ROM Mode 2):#############################################################################################i i2cstd#mclk expected is 24.576 MHz#configuring device registers for 8 ohm speaker load########################### DEVICE INIT SEQ START##############################################w 98 00 00 #Page-0w 98 7f 00 #Book-0w 98 01 01 #Software reset d 1 # wait 100us time for OTP-One Time Programmable memory values to be transferred to device ##### DSP PROG SETTING STARTw 98 22 22 # use default coefficients and operate DSP in rom mode 2##### DSP PROG SETTING END########################### DEVICE INIT SEQ END ################################################################## CHANNEL POWER UP ####################################################w 98 05 A3 # Power up Analog Blocksw 98 04 B8 # Power up DSP and clock dividersw 98 07 00 # Unmute Analog Blocksw 98 7f 64 # switch to book100w 98 07 00 # Soft stepped unmute of audio playback################################################################################################# DSP coeff update START# d 1# DSP filter coefficient update if required##### DSP coeff update ENDb ############device powered up and running##########

Device Mute and Power Down Sequence

The following code example provide the correct sequence to mute and power down the device. The PurePath Console 3 Software TAS2557 Application software will create output files with these commands.

Example script (ROM Mode 2):#############################################################################################i i2cstd################### CHANNEL POWER DOWN ####################################################w 98 07 01 # Soft stepped mute of audio playbackd 10 # wait for DSP to mute classD after soft step down of audio# instead of delay alternatively status flag B120_P15_R120_R121_R122_R123 polling can be done and wait till R122_D0 = '1'.w 98 7f 00 # switch to book0w 98 07 03 # Mute Analog Blocksw 98 04 20 # Power down DSP and clock dividers (except Ndivider)w 98 05 00 # Power down Analog Blocks w 98 00 00 # NOP w 98 04 00 # Power down Ndivider ##############################################################################################optional(ending the script in B0_P0)w 98 00 00 # page 0w 98 7f 00 # book 0#############################################################################################