ZHCSGI2B July 2017 – October 2018 TAS2505-Q1
请参考 PDF 数据表获取器件具体的封装图。
The TAS2505-Q1 supports a wide range of options for generating clocks for the DAC sections as well as interface and other control blocks. The clocks for the DAC require a source reference clock. This clock can be provided on a variety of device pins, such as the MCLK, BCLK, or GPIO pins. The source reference clock for the codec can be chosen by programming the CODEC_CLKIN value on page 0, register 4, bits D1–D0. The CODEC_CLKIN can then be routed through highly-flexible clock dividers shown in Figure 2 through 7 in the TAS2505 Application Reference Guide to generate the various clocks required for the DAC and the Digital Effects section also found in the TAS2505 Application Reference Guide (SLAU472). In the event that the desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO, the TAS2505-Q1 also provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN, the TAS2505-Q1 provides several programmable clock dividers to help achieve a variety of sampling rates for the DAC and clocks for the Digital Effects sections.
For more detailed information see the TAS2505 Application Reference Guide (SLAU472).