8.2.1.1 Design Requirements

The design requirements are as follows:

• Supply Voltage: 5-V DC
• Input: 0-V to 2-V DC
• Output: 0-mA to 10-mA DC

8.2.1.2 Detailed Design Procedure

The V-I transfer function of the circuit is based on the relationship between the input voltage, V_IN, and the three current sensing resistors, R_S1, R_S2, and R_S3. The relationship between V_IN and R_S1 determines the current that flows through the first stage of the design. The current gain from the first stage to the second stage is based on the relationship between R_S2 and R_S3.

For a successful design, pay close attention to the DC characteristics of the operational amplifier chosen for the application. To meet the performance goals, this application benefits from an operational amplifier with low offset voltage, low temperature drift, and rail-to-rail output. The OPA2333 CMOS operational amplifier is a high-precision, 5-µV offset, 0.05-μV/°C drift amplifier optimized for low-voltage, single-supply operation with an output swing to within 50 mV of the positive rail. The OPA2333 family uses chopping techniques to provide low initial offset voltage and near-zero drift over time and temperature. Low offset voltage and low drift reduce the offset error in the system, making these devices appropriate for precise DC control. The rail-to-rail output stage of the OPA2333 ensures that the output swing of the operational amplifier is able to fully control the gate of the MOSFET devices within the supply rails.

See TIPD102 for a detailed error analysis, design procedure, and additional measured results.

8.2.1.3 Application Curve

Figure 23. Measured Transfer Function for High-Side V-I Converter

8.2.2.1 Design Requirements

The design requirements are as follows:

• Supply Voltage: 5-V DC
• Input: 0-V to 5-V DC
• Output: 0-μA to 5-μA DC

8.2.2.2 Detailed Design Procedure

The V-I transfer function of the circuit is based on the relationship between the input voltage, V_IN, R_SET, and the instrumentation amplifier (INA) gain. During operation, the input voltage divided by the INA gain appears across the set resistor in Equation 1:

The current through R_SET must flow through the load, so I_OUT is V_SET / R_SET. I_OUT remains a well-regulated current as long as the total voltage across R_SET and R_LOAD does not violate the output limits of the operational amplifier or the input common-mode limits of the INA. The voltage across the set resistor (V_SET) is the input voltage divided by the INA gain (that is, V_SET = 1 V / 10 = 0.1 V). The current is determined by V_SET and R_SET shown in Equation 2:

See TIPD107 for a detailed error analysis, design procedure, and additional measured results.

8.2.2.3 Application Curves

Figure 25. Measured Transfer Function for Low-Level Precision V-I

Figure 26. Calibrated Output Error for Low-Level V-I

8.2.3.1 Design Requirements

The design requirements for this block design are:

• System Supply Voltage: 5-V DC
• ADC Supply Voltage: 3.3-V DC
• ADC Sampling Rate: 1 MSPS
• ADC Reference Voltage (VREF): 4.5-V DC
• ADC Input Signal: A differential input signal with amplitude of V_pk = 4.315 V (–0.4 dBFS to avoid clipping) and frequency, f_IN = 10 kHz are applied to each differential input of the ADC

8.2.3.2 Detailed Design Procedure

The two primary design considerations to maximize the performance of a high-resolution SAR ADC are the input driver and the reference driver design. The circuit comprises the critical analog circuit blocks, the input driver, anti-aliasing filter, and the reference driver. Each analog circuit block should be carefully designed based on the ADC performance specifications in order to maximize the distortion and noise performance of the data acquisition system while consuming low power. The diagram includes the most important specifications for each individual analog block. This design systematically approaches the design of each analog circuit block to achieve a 16-bit, low-noise and low-distortion data acquisition system for a 10-kHz sinusoidal input signal. The first step in the design requires an understanding of the requirement of extremely low distortion input driver amplifier. This understanding helps in the decision of an appropriate input driver configuration and selection of an input amplifier to meet the system requirements. The next important step is the design of the anti-aliasing RC-filter to attenuate ADC kick-back noise while maintaining the amplifier stability. The final design challenge is to design a high-precision reference driver circuit, which would provide the required value VREF with low offset, drift, and noise contributions.

In designing a very low distortion data acquisition block, it is important to understand the sources of nonlinearity. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. To achieve the lowest distortion, the input driver for a high-performance SAR ADC must have a distortion that is negligible against the ADC distortion. This parameter requires the input driver distortion to be 10 dB lower than the ADC THD. This stringent requirement ensures that overall THD of the system is not degraded by more than –0.5 dB.

It is therefore important to choose an amplifier that meets the above criteria to avoid the system THD from being limited by the input driver. The amplifier nonlinearity in a feedback system depends on the available loop gain. See TIPD115 for a detailed error analysis, design procedure, and additional measured results.

8.2.3.3 Application Curve

Figure 28. Linearity of the ADC8881 System