ZHCSHI9B December   2017  – June 2019 MSP432P4011T , MSP432P401VT , MSP432P401YT , MSP432P4111T , MSP432P411VT , MSP432P411YT

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram for MSP432P411xT Devices
    2. 4.2 Pin Diagram for MSP432P401xT Devices
    3. 4.3 Pin Attributes
    4. 4.4 Signal Descriptions
      1. Table 4-3 Signal Descriptions
    5. 4.5 Pin Multiplexing
    6. 4.6 Buffer Types
    7. 4.7 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Recommended External Components
    5. 5.5  Operating Mode VCC Ranges
    6. 5.6  Operating Mode CPU Frequency Ranges
    7. 5.7  Operating Mode Peripheral Frequency Ranges
    8. 5.8  Operating Mode Execution Frequency and Flash Wait-State Requirements
    9. 5.9  Current Consumption During Device Reset of the 100-Pin LQFP Package
    10. 5.10 Current Consumption in LDO-Based Active Modes – Dhrystone 2.1 Program
    11. 5.11 Current Consumption in DC/DC-Based Active Modes – Dhrystone 2.1 Program
    12. 5.12 Current Consumption in Low-Frequency Active Modes – Dhrystone 2.1 Program
    13. 5.13 Typical Characteristics of Active Mode Currents for CoreMark Program
    14. 5.14 Typical Characteristics of Active Mode Currents for Prime Number Program
    15. 5.15 Typical Characteristics of Active Mode Currents for Fibonacci Program
    16. 5.16 Typical Characteristics of Active Mode Currents for While(1) Program
    17. 5.17 Typical Characteristics of Low-Frequency Active Mode Currents for CoreMark Program
    18. 5.18 Current Consumption in LDO-Based LPM0 Modes
    19. 5.19 Current Consumption in DC/DC-Based LPM0 Modes
    20. 5.20 Current Consumption in Low-Frequency LPM0 Modes
    21. 5.21 Current Consumption in LPM3, LPM4 Modes
    22. 5.22 Current Consumption in LPM3 Modes With LCD
    23. 5.23 Current Consumption in LPM3.5, LPM4.5 Modes
    24. 5.24 Current Consumption of Digital Peripherals
    25. 5.25 Thermal Resistance Characteristics
    26. 5.26 Timing and Switching Characteristics
      1. 5.26.1  Reset Timing
        1. Table 5-1 Reset Recovery Latencies
        2. Table 5-2 External Reset Recovery Latencies
      2. 5.26.2  Peripheral Register Access Timing
        1. Table 5-3 Peripheral Register Access Latency
      3. 5.26.3  Mode Transition Timing
        1. Table 5-4 Active Mode Transition Latencies
        2. Table 5-5 LPM0 Mode Transition Latencies
        3. Table 5-6 LPM3, LPM4 Mode Transition Latencies
        4. Table 5-7 LPM3.5, LPM4.5 Mode Transition Latencies
      4. 5.26.4  Clock Specifications
        1. Table 5-8  Low-Frequency Crystal Oscillator, LFXT, Recommended Operating Conditions
        2. Table 5-9  Low-Frequency Crystal Oscillator, LFXT
        3. Table 5-10 High-Frequency Crystal Oscillator, HFXT, Recommended Operating Conditions
        4. Table 5-11 High-Frequency Crystal Oscillator, HFXT
        5. Table 5-12 DCO
        6. Table 5-13 DCO Overall Tolerance
        7. Table 5-14 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        8. Table 5-15 Internal-Reference Low-Frequency Oscillator (REFO) – 32.768-kHz Mode
        9. Table 5-16 Internal-Reference Low-Frequency Oscillator (REFO) – 128-kHz Mode
        10. Table 5-17 Module Oscillator (MODOSC)
        11. Table 5-18 System Oscillator (SYSOSC)
      5. 5.26.5  Power Supply System
        1. Table 5-19 VCORE Regulator (LDO) Characteristics
        2. Table 5-20 VCORE Regulator (DC/DC) Characteristics
        3. Table 5-21 PSS, VCCDET
        4. Table 5-22 PSS, SVSMH
      6. 5.26.6  Digital I/Os
        1. Table 5-23 Digital Inputs (Applies to Both Normal and High-Drive I/Os)
        2. Table 5-24 Digital Outputs, Normal I/Os
        3. Table 5-25 Digital Outputs, High-Drive I/Os
        4. Table 5-26 Pin-Oscillator Frequency, Ports Px
        5. 5.26.6.1   Typical Characteristics, Normal-Drive I/O Outputs at 3.0 V and 2.2 V
        6. 5.26.6.2   Typical Characteristics, High-Drive I/O Outputs at 3.0 V and 2.2 V
        7. 5.26.6.3   Typical Characteristics, Pin-Oscillator Frequency
      7. 5.26.7  Precision ADC
        1. Table 5-27 14-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-28 14-Bit ADC, Timing Parameters
        3. Table 5-29 14-Bit ADC, Linearity Parameters
        4. Table 5-30 14-Bit ADC, Dynamic Parameters
        5. Table 5-31 14-Bit ADC, Temperature Sensor and Built-In V1/2
        6. Table 5-32 14-Bit ADC, Internal Reference Buffers
        7. Table 5-33 14-Bit ADC, External Reference
        8. 5.26.7.1   Typical Characteristics of ADC
      8. 5.26.8  REF_A
        1. Table 5-35 REF_A, Built-In Reference
      9. 5.26.9  Comparator_E
        1. Table 5-36 Comparator_E Characteristics
      10. 5.26.10 LCD_F
        1. Table 5-37 LCD Recommended Operating Conditions
        2. Table 5-38 LCD Electrical Characteristics
      11. 5.26.11 eUSCI
        1. Table 5-39 eUSCI Clock Frequency (UART Mode)
        2. Table 5-40 eUSCI Switching Characteristics (UART Mode)
        3. Table 5-41 eUSCI Clock Frequency (SPI Master Mode)
        4. Table 5-42 eUSCI Switching Characteristics (SPI Master Mode)
        5. Table 5-43 eUSCI Switching Characteristics (SPI Slave Mode)
        6. Table 5-44 eUSCI Clock Frequency (I2C Mode)
        7. Table 5-45 eUSCI Switching Characteristics (I2C Mode)
      12. 5.26.12 Timer_A
        1. Table 5-46 Timer_A Characteristics
        2. Table 5-47 Timer32 Characteristics
      13. 5.26.13 Memories
        1. Table 5-48 Flash Memory Characteristics
        2. Table 5-49 Flash Characteristics for Operations Using MSP432 Peripheral Driver Libraries
        3. Table 5-50 Flash Characteristics for Stand-Alone Operations
        4. Table 5-51 SRAM Characteristics
      14. 5.26.14 Emulation and Debug
        1. Table 5-52 JTAG Timing Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Processor and Execution Features
      1. 6.2.1 Floating-Point Unit (FPU)
      2. 6.2.2 Memory Protection Unit (MPU)
      3. 6.2.3 Nested Vectored Interrupt Controller (NVIC)
      4. 6.2.4 SysTick
      5. 6.2.5 Debug and Trace Features
    3. 6.3  Memory Map
      1. 6.3.1 Code Zone Memory Map
        1. 6.3.1.1 Flash Memory Region
        2. 6.3.1.2 SRAM Region
        3. 6.3.1.3 ROM Region
      2. 6.3.2 SRAM Zone Memory Map
        1. 6.3.2.1 SRAM Region
        2. 6.3.2.2 SRAM Bit-Band Alias Region
      3. 6.3.3 Peripheral Zone Memory Map
        1. 6.3.3.1 Peripheral Region
        2. 6.3.3.2 Peripheral Bit Band Alias Region
      4. 6.3.4 Debug and Trace Peripheral Zone
    4. 6.4  Memories on MSP432P4x1xT
      1. 6.4.1 Flash Memory
        1. 6.4.1.1 Flash Main Memory (0x0000_0000 to 0x001F_FFFF)
        2. 6.4.1.2 Flash Information Memory (0x0020_0000 to 0x0020_7FFF)
        3. 6.4.1.3 Flash Operation
      2. 6.4.2 SRAM
        1. 6.4.2.1 SRAM Bank Enable Configuration
        2. 6.4.2.2 SRAM Block Retention Configuration and Backup Memory
        3. 6.4.2.3 Utility SRAM
      3. 6.4.3 ROM
    5. 6.5  DMA
      1. 6.5.1 DMA Source Mapping
      2. 6.5.2 DMA Completion Interrupts
      3. 6.5.3 DMA Access Privileges
    6. 6.6  Memory Map Access Details
      1. 6.6.1 Master and Slave Access Priority Settings
      2. 6.6.2 Memory Map Access Response
    7. 6.7  Interrupts
      1. 6.7.1 NMI
      2. 6.7.2 Device-Level User Interrupts
    8. 6.8  System Control
      1. 6.8.1 Device Resets
        1. 6.8.1.1 Power On/Off Reset (POR)
        2. 6.8.1.2 Reboot Reset
        3. 6.8.1.3 Hard Reset
        4. 6.8.1.4 Soft Reset
      2. 6.8.2 Power Supply System (PSS)
        1. 6.8.2.1 VCCDET
        2. 6.8.2.2 Supply Supervisor and Monitor for High Side (SVSMH)
        3. 6.8.2.3 Core Voltage Regulator
      3. 6.8.3 Power Control Manager (PCM)
        1. 6.8.3.1 Peripherals in LPM3 and LPM4
      4. 6.8.4 Clock System (CS)
        1. 6.8.4.1 LFXT
        2. 6.8.4.2 HFXT
        3. 6.8.4.3 DCO
        4. 6.8.4.4 Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 6.8.4.5 Low-Frequency Reference Oscillator (REFO)
        6. 6.8.4.6 Module Oscillator (MODOSC)
        7. 6.8.4.7 System Oscillator (SYSOSC)
        8. 6.8.4.8 Fail-Safe Mechanisms
      5. 6.8.5 System Controller (SYSCTL_A)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
        1. 6.9.1.1 Glitch Filtering on Digital I/Os
      2. 6.9.2  Port Mapping Controller (PMAPCTL)
        1. 6.9.2.1 Port Mapping Definitions
      3. 6.9.3  Timer_A
        1. 6.9.3.1 Timer_A Signal Connection Tables
      4. 6.9.4  Timer32
      5. 6.9.5  Enhanced Universal Serial Communication Interface (eUSCI)
      6. 6.9.6  Real-Time Clock (RTC_C)
      7. 6.9.7  Watchdog Timer (WDT_A)
      8. 6.9.8  Precision ADC
      9. 6.9.9  Comparator_E (COMP_E)
      10. 6.9.10 Shared Reference (REF_A)
      11. 6.9.11 LCD Controller (LCD_F)
      12. 6.9.12 CRC32
      13. 6.9.13 AES256 Accelerator
      14. 6.9.14 True Random Seed
    10. 6.10 Code Development and Debug
      1. 6.10.1 JTAG and Serial Wire Debug (SWD) Based Development, Debug, and Trace
      2. 6.10.2 Peripheral Halt Control
      3. 6.10.3 Bootloader (BSL)
      4. 6.10.4 Device Security
    11. 6.11 Performance Benchmarks
      1. 6.11.1 CoreMark/MHz Performance: 3.41
      2. 6.11.2 DMIPS/MHz (Dhrystone 2.1) Performance: 1.196
    12. 6.12 Input/Output Schematics
      1. 6.12.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
      2. 6.12.2  Port P2, P2.0 to P2.3, Input/Output With Schmitt Trigger
      3. 6.12.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
      4. 6.12.4  Port P9, P9.4 to P9.7, Input/Output With Schmitt Trigger
      5. 6.12.5  Port P10, P10.0 to P10.3, Input/Output With Schmitt Trigger
      6. 6.12.6  Port P2, P2.4 to P2.7, Input/Output With Schmitt Trigger
      7. 6.12.7  Port P7, P7.0 to P7.2, Input/Output With Schmitt Trigger
      8. 6.12.8  Port P7, P7.3, Input/Output With Schmitt Trigger
      9. 6.12.9  Port P9, P9.2 and P9.3, Input/Output With Schmitt Trigger
      10. 6.12.10 Port P4, P4.2 to P4.7, Input/Output With Schmitt Trigger
      11. 6.12.11 Port P5, P5.0 to P5.5, Input/Output With Schmitt Trigger
      12. 6.12.12 Port P4, P4.0 to P4.1, Input/Output With Schmitt Trigger
      13. 6.12.13 Port P6, P6.0 and P6.1, Input/Output With Schmitt Trigger
      14. 6.12.14 Port P8, P8.2 to P8.7, Input/Output With Schmitt Trigger
      15. 6.12.15 Port P9, P9.0 and P9.1, Input/Output With Schmitt Trigger
      16. 6.12.16 Port P5, P5.6 and P5.7, Input/Output With Schmitt Trigger
      17. 6.12.17 Port P6, P6.2 to P6.5, Input/Output With Schmitt Trigger
      18. 6.12.18 Port P6, P6.6 and P6.7, Input/Output With Schmitt Trigger
      19. 6.12.19 Port P8, P8.0 and P8.1, Input/Output With Schmitt Trigger
      20. 6.12.20 Port P10, P10.4 and P10.5, Input/Output With Schmitt Trigger
      21. 6.12.21 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
      22. 6.12.22 Port PJ, PJ.0 and PJ.1 Input/Output With Schmitt Trigger
      23. 6.12.23 Port PJ, PJ.2 and PJ.3 Input/Output With Schmitt Trigger
      24. 6.12.24 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
      25. 6.12.25 Ports SWCLKTCK and SWDIOTMS With Schmitt Trigger
    13. 6.13 Device Descriptors (TLV)
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 Arm Cortex-M4F ROM Table Based Part Number
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 General Layout Recommendations
      4. 7.1.4 Do's and Don'ts
    2. 7.2 Peripheral and Interface-Specific Design Information
      1. 7.2.1 Precision ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1  开始使用
    2. 8.2  器件命名规则
    3. 8.3  工具与软件
    4. 8.4  文档支持
    5. 8.5  相关链接
    6. 8.6  社区资源
    7. 8.7  商标
    8. 8.8  静电放电警告
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PZ|100
散热焊盘机械数据 (封装 | 引脚)
订购信息

Port Mapping Definitions

The port mapping controller on MSP432P4x1xT devices allows reconfigurable mapping of digital functions on ports P2, P3, and P7.

Table 6-46 Port Mapping Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
1 PM_UCA0CLK eUSCI_A0 clock input/output (direction controlled by eUSCI)
2 PM_UCA0RXD eUSCI_A0 UART RXD (direction controlled by eUSCI – input)
PM_UCA0SOMI eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
3 PM_UCA0TXD eUSCI_A0 UART TXD (direction controlled by eUSCI – output)
PM_UCA0SIMO eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
4 PM_UCB0CLK eUSCI_B0 clock input/output (direction controlled by eUSCI)
5 PM_UCB0SDA eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
PM_UCB0SIMO eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
6 PM_UCB0SCL eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
PM_UCB0SOMI eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
7 PM_UCA1STE eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
8 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI)
9 PM_UCA1RXD eUSCI_A1 UART RXD (direction controlled by eUSCI – input)
PM_UCA1SOMI eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
10 PM_UCA1TXD eUSCI_A1 UART TXD (direction controlled by eUSCI – output)
PM_UCA1SIMO eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
11 PM_UCA2STE eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
12 PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI)
13 PM_UCA2RXD eUSCI_A2 UART RXD (direction controlled by eUSCI – input)
PM_UCA2SOMI eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
14 PM_UCA2TXD eUSCI_A2 UART TXD (direction controlled by eUSCI – output)
PM_ UCA2SIMO eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
15 PM_UCB2STE eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI)
16 PM_UCB2CLK eUSCI_B2 clock input/output (direction controlled by eUSCI)
17 PM_UCB2SDA eUSCI_B2 I2C data (open drain and direction controlled by eUSCI)
PM_UCB2SIMO eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)
18 PM_UCB2SCL eUSCI_B2 I2C clock (open drain and direction controlled by eUSCI)
PM_UCB2SOMI eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)
19 PM_TA0CCR0A TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
20 PM_TA0CCR1A TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
21 PM_TA0CCR2A TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
22 PM_TA0CCR3A TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3
23 PM_TA0CCR4A TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4
24 PM_TA1CCR1A TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
25 PM_TA1CCR2A TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2
26 PM_TA1CCR3A TA1 CCR3 capture input CCI3A TA1 CCR3 compare output Out3
27 PM_TA1CCR4A TA1 CCR4 capture input CCI4A TA1 CCR4 compare output Out4
28 PM_TA0CLK Timer_A0 external clock input None
PM_C0OUT None Comparator-E0 output
29 PM_TA1CLK Timer_A1 external clock input None
PM_C1OUT None Comparator-E1 output
30 PM_DMAE0 DMAE0 input None
PM_SMCLK None SMCLK
31 (0FFh)(1) PM_ANALOG Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.
The value of the PM_ANALOG mnemonic is 31. The port mapping registers are 5 bits wide, and the upper bits are ignored, which results in a read value of 31.

Table 6-47 Default Mapping

PIN NAME PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
P2.0/PM_UCA1STE/L11 PM_UCA1STE eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
P2.1/PM_UCA1CLK/L10 PM_UCA1CLK eUSCI_A1 clock input/output (direction controlled by eUSCI)
P2.2/PM_UCA1RXD/ PM_UCA1SOMI/L9 PM_UCA1RXD/
PM_UCA1SOMI
eUSCI_A1 UART RXD (direction controlled by eUSCI – Input)
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
P2.3/PM_UCA1TXD/ PM_UCA1SIMO/L8 PM_UCA1TXD/
PM_UCA1SIMO
eUSCI_A1 UART TXD (direction controlled by eUSCI – output)/
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
P2.4/PM_TA0.1/L23(1) PM_TA0CCR1A TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1
P2.5/PM_TA0.2/L22(1) PM_TA0CCR2A TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2
P2.6/PM_TA0.3/L21(1) PM_TA0CCR3A TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3
P2.7/PM_TA0.4/L20(1) PM_TA0CCR4A TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4
P3.0/PM_UCA2STE/L7 PM_UCA2STE eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
P3.1/PM_UCA2CLK/L6 PM_UCA2CLK eUSCI_A2 clock input/output (direction controlled by eUSCI)
P3.2/PM_UCA2RXD/ PM_UCA2SOMI/L5 PM_UCA2RXD/
PM_UCA2SOMI
eUSCI_A2 UART RXD (direction controlled by eUSCI – input)/
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
P3.3/PM_UCA2TXD/ PM_UCA2SIMO/L4 PM_UCA2TXD/
PM_UCA2SIMO
eUSCI_A2 UART TXD (direction controlled by eUSCI – output)/
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
P3.4/PM_UCB2STE/L3 PM_UCB2STE eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI)
P3.5/PM_UCB2CLK/L2 PM_UCB2CLK eUSCI_B2 clock input/output (direction controlled by eUSCI)
P3.6/PM_UCB2SIMO/ PM_UCB2SDA/L1 PM_UCB2SIMO/
PM_UCB2SDA
eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)/
eUSCI_B2 I2C data (open drain and direction controlled by eUSCI)
P3.7/PM_UCB2SOMI/ PM_UCB2SCL/L0 PM_UCB2SOMI/
PM_UCB2SCL
eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)/
eUSCI_B2 I2C clock (open drain and direction controlled by eUSCI)
P7.0/PM_SMCLK/ PM_DMAE0/R03 PM_SMCLK/
PM_DMAE0
DMAE0 input SMCLK
P7.1/PM_C0OUT/ PM_TA0CLK/R13/LCDREF PM_C0OUT/
PM_TA0CLK
Timer_A0 external clock input Comparator-E0 output
P7.2/PM_C1OUT/ PM_TA1CLK/R23 PM_C1OUT/
PM_TA1CLK
Timer_A1 external clock input Comparator-E1 output
P7.3/PM_TA0.0/R33/LCDCAP PM_TA0CCR0A TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0
P7.4/PM_TA1.4/C0.5/L31(1) PM_TA1CCR4A TA1 CCR4 capture input CCI4A TA1 CCR4 compare output Out4
P7.5/PM_TA1.3/C0.4/L30(1) PM_TA1CCR3A TA1 CCR3 capture input CCI3A TA1 CCR3 compare output Out3
P7.6/PM_TA1.2/C0.3/L29(1) PM_TA1CCR2A TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2
P7.7/PM_TA1.1/C0.2/L28(1) PM_TA1CCR1A TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1
Not available on the 64-pin RGC package.