The application can optimize the power consumption of the SRAM. To enable this, the SRAM is divided into 64-KB banks that can be individually powered down. Banks that are powered down remain powered down in both active and low-power modes of operation, thereby limiting any unnecessary inrush current when the device transitions between active and retention-based low-power modes. The application can also disable one (or more) banks for a certain stage in the processing and enable it for another stage.
When a particular bank is disabled, reads to its address space return 0h, and writes are discarded. To prevent holes in the memory map, if a particular bank is enabled, all the lower banks are also forced to enabled state. This ensures a contiguous memory map through the set of enabled banks, instead of a allowing a disabled bank to appear between enabled banks. For example:
Figure 6-7 shows valid and invalid combinations of bank enable settings.
Bank 0 of SRAM is always enabled and cannot be disabled. For all other banks, any enable or disable change results in the BNKEN_RDY bit of the SYS_SRAM_STAT register being set to 0 until the configuration change is effective. Accesses to the SRAM is stalled during this time and resumes only after the SRAM banks are ready for read or write operations. This is handled transparently and does not require any code intervention. See Table 5-51 for the SRAM bank enable or disable latency.