ZHCSEA0E October   2015  – August 2019 MSP430FR2433

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1       Absolute Maximum Ratings
    2. 5.2       ESD Ratings
    3. 5.3       Recommended Operating Conditions
    4. 5.4       Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5       Active Mode Supply Current Per MHz
    6. 5.6       Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7       Low-Power Mode (LPM3 and LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8       Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 5.9       Typical Characteristics - Low-Power Mode Supply Currents
    10. Table 5-1 Typical Characteristics – Current Consumption Per Module
    11. 5.10      Thermal Resistance Characteristics
    12. 5.11      Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. Table 5-2 PMM, SVS and BOR
      2. 5.11.2  Reset Timing
        1. Table 5-3 Wake-up Times From Low-Power Modes and Reset
      3. 5.11.3  Clock Specifications
        1. Table 5-4 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-5 DCO FLL, Frequency
        3. Table 5-6 DCO Frequency
        4. Table 5-7 REFO
        5. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-9 Module Oscillator (MODOSC)
      4. 5.11.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.11.4.1   Typical Characteristics – Outputs at 3 V and 2 V
      5. 5.11.5  VREF+ Built-in Reference
        1. Table 5-12 VREF+
      6. 5.11.6  Timer_A
        1. Table 5-13 Timer_A
      7. 5.11.7  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequency
        2. Table 5-15 eUSCI (UART Mode)
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode)
        5. Table 5-18 eUSCI (SPI Slave Mode)
        6. Table 5-19 eUSCI (I2C Mode)
      8. 5.11.8  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, 10-Bit Timing Parameters
        3. Table 5-22 ADC, 10-Bit Linearity Parameters
      9. 5.11.9  FRAM
        1. Table 5-23 FRAM
      10. 5.11.10 Debug and Emulation
        1. Table 5-24 JTAG, Spy-Bi-Wire Interface
        2. Table 5-25 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Standard Interface
    7. 6.7  Spy-Bi-Wire Interface (SBW)
    8. 6.8  FRAM
    9. 6.9  Memory Protection
    10. 6.10 Peripherals
      1. 6.10.1  Power-Management Module (PMM)
      2. 6.10.2  Clock System (CS) and Clock Distribution
      3. 6.10.3  General-Purpose Input/Output Port (I/O)
      4. 6.10.4  Watchdog Timer (WDT)
      5. 6.10.5  System (SYS) Module
      6. 6.10.6  Cyclic Redundancy Check (CRC)
      7. 6.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.10.8  Timers (Timer0_A3, Timer1_A3, Timer2_A2 and Timer3_A2)
      9. 6.10.9  Hardware Multiplier (MPY)
      10. 6.10.10 Backup Memory (BAKMEM)
      11. 6.10.11 Real-Time Clock (RTC)
      12. 6.10.12 10-Bit Analog-to-Digital Converter (ADC)
      13. 6.10.13 Embedded Emulation Module (EEM)
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1 Input/Output With Schmitt Trigger
      2. 6.11.2 Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      3. 6.11.3 Port P2 (P2.3 to P2.7) Input/Output With Schmitt Trigger
      4. 6.11.4 Port P3 (P3.0 to P3.2) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors
    13. 6.13 Memory
      1. 6.13.1 Memory Organization
      2. 6.13.2 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和后续步骤
    2. 8.2 器件命名规则
    3. 8.3 工具与软件
    4. 8.4 文档支持
    5. 8.5 社区资源
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

特性

  • 嵌入式微控制器
    • 16 位 RISC 架构
    • 支持的时钟频率最高可达 16MHz
    • 3.6V 至 1.8V 的宽电源电压范围(最低电源电压受限于 SVS 电平,请参阅 SVS 规格
  • 优化的超低功耗模式
    • 激活模式:126µA/MHz(典型值)
    • 待机模式:VLO 的电流小于 1µA
    • 采用 32768Hz 晶振的 LPM3.5 实时时钟 (RTC) 计数器:730nA(典型值)
    • 关断电流 (LPM4.5):16nA(典型值)
  • 高性能模拟
    • 8 通道 10 位模数转换器 (ADC)
      • 1.5V 的内部基准电压
      • 采样与保持 200ksps
  • 增强型串行通信
    • 两个增强型通用串行通信接口 (eUSCI_A) 支持 UART、IrDA 和 SPI
    • 一个 eUSCI (eUSCI_B) 支持 SPI 和 I2C
  • 智能数字外设
    • 四个 16 位计时器
      • 两个计时器,每个计时器具有三个捕捉/比较寄存器 (Timer_A3)
      • 两个计时器,每个计时器具有两个捕捉/比较寄存器 (Timer_A2)
    • 一个仅用作计数器的 16 位 RTC
    • 16 位循环冗余校验 (CRC)
  • 低功耗铁电 RAM (FRAM)
    • 容量高达 15.5KB 的非易失性存储器
    • 内置错误修正码 (ECC)
    • 可配置的写保护
    • 对程序、常量和存储的统一存储
    • 耐写次数达 1015
    • 抗辐射和非磁性
    • FRAM 与 SRAM 之比高达 4:1
  • 时钟系统 (CS)
    • 片上 32kHz RC 振荡器 (REFO)
    • 带有锁频环 (FLL) 的片上 16MHz 数控振荡器 (DCO)
      • 室温下的精度为 ±1%(具有片上基准)
    • 片上超低频 10kHz 振荡器 (VLO)
    • 片上高频调制振荡器 (MODOSC)
    • 外部 32kHz 晶振 (LFXT)
    • 可编程 MCLK 预分频器(1 至 128)
    • 通过可编程预分频器(1、2、4 或 8)从 MCLK 获得的 SMCLK
  • 通用输入/输出和引脚功能
    • 共计 19 个 I/O(采用 VQFN-24 封装)
    • 16 个中断引脚(P1 和 P2)可以将 MCU 从低功耗模式下唤醒
  • 开发工具和软件
  • 系列成员(另请参阅器件比较
    • MSP430FR2433:15KB 程序 FRAM、512B 信息 FRAM、4KB RAM
  • 封装选项
    • 24 引脚:VQFN (RGE)
    • 24 引脚:DSBGA (YQW)