ZHCSFC7C August   2016  – August 2018 MSP430FR2000 , MSP430FR2100 , MSP430FR2110 , MSP430FR2111

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Connection of Unused Pins
    6. 4.6 Buffer Type
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Active Mode Supply Current Per MHz
    6. 5.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Typical Characteristics – LPM3 Supply Currents
    9. 5.9  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics – LPMx.5 Supply Currents
    11. 5.11 Typical Characteristics - Current Consumption Per Module
    12. 5.12 Thermal Resistance Characteristics
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1  Power Supply Sequencing
        1. Table 5-1 PMM, SVS and BOR
      2. 5.13.2  Reset Timing
        1. Table 5-2 Wake-up Times From Low-Power Modes and Reset
      3. 5.13.3  Clock Specifications
        1. Table 5-3 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-4 DCO FLL, Frequency
        3. Table 5-5 DCO Frequency
        4. Table 5-6 REFO
        5. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4  Digital I/Os
        1. Table 5-9  Digital Inputs
        2. Table 5-10 Digital Outputs
        3. 5.13.4.1   Digital I/O Typical Characteristics
      5. 5.13.5  VREF+ Built-in Reference
        1. Table 5-11 VREF+ Characteristics
      6. 5.13.6  Timer_B
        1. Table 5-12 Timer_B Clock Frequency
      7. 5.13.7  eUSCI
        1. Table 5-13 eUSCI (UART Mode) Clock Frequency
        2. Table 5-14 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-15 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-16 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-17 eUSCI (SPI Slave Mode) Switching Characteristics
      8. 5.13.8  ADC
        1. Table 5-18 ADC, Power Supply and Input Range Conditions
        2. Table 5-19 ADC, 10-Bit Timing Parameters
        3. Table 5-20 ADC, 10-Bit Linearity Parameters
      9. 5.13.9  Enhanced Comparator (eCOMP)
        1. Table 5-21 eCOMP
      10. 5.13.10 FRAM
        1. Table 5-22 FRAM
      11. 5.13.11 Emulation and Debug
        1. Table 5-23 JTAG, Spy-Bi-Wire Interface
        2. Table 5-24 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Standard Interface
    8. 6.8  Spy-Bi-Wire Interface (SBW)
    9. 6.9  FRAM
    10. 6.10 Memory Protection
    11. 6.11 Peripherals
      1. 6.11.1  Power-Management Module (PMM) and On-Chip Reference Voltages
      2. 6.11.2  Clock System (CS) and Clock Distribution
      3. 6.11.3  General-Purpose Input/Output Port (I/O)
      4. 6.11.4  Watchdog Timer (WDT)
      5. 6.11.5  System Module (SYS)
      6. 6.11.6  Cyclic Redundancy Check (CRC)
      7. 6.11.7  Enhanced Universal Serial Communication Interface (eUSCI_A0)
      8. 6.11.8  Timers (Timer0_B3)
      9. 6.11.9  Backup Memory (BAKMEM)
      10. 6.11.10 Real-Time Clock (RTC) Counter
      11. 6.11.11 10-Bit Analog-to-Digital Converter (ADC)
      12. 6.11.12 eCOMP0
      13. 6.11.13 Embedded Emulation Module (EEM)
      14. 6.11.14 Peripheral File Map
      15. 6.11.15 Input/Output Diagrams
        1. 6.11.15.1 Port P1 Input/Output With Schmitt Trigger
        2. 6.11.15.2 Port P2 Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors (TLV)
    13. 6.13 Identification
      1. 6.13.1 Revision Identification
      2. 6.13.2 Device Identification
      3. 6.13.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
    3. 7.3 Typical Applications
  8. 8器件和文档支持
    1. 8.1 入门和后续步骤
    2. 8.2 器件命名规则
    3. 8.3 工具与软件
    4. 8.4 文档支持
    5. 8.5 相关链接
    6. 8.6 社区资源
    7. 8.7 商标
    8. 8.8 静电放电警告
    9. 8.9 术语表
  9. 9机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
订购信息

器件概述