ZHCSER2D May   2013  – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
    8. 8.8  Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
    9. 8.9  Inputs – Interrupts DVCC Domain Port P6 (P6.0 to P6.7)
    10. 8.10 Inputs – Interrupts DVIO Domain Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    11. 8.11 Leakage Current – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 8.12 Leakage Current – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    13. 8.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    14. 8.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    15. 8.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    16. 8.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    17. 8.17 Output Frequency – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    18. 8.18 Output Frequency – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    19. 8.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    20. 8.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    21. 8.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 8.22 Crystal Oscillator, XT2
    23. 8.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 8.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 8.25 DCO Frequency
    26. 8.26 PMM, Brownout Reset (BOR)
    27. 8.27 PMM, Core Voltage
    28. 8.28 PMM, SVS High Side
    29. 8.29 PMM, SVM High Side
    30. 8.30 PMM, SVS Low Side
    31. 8.31 PMM, SVM Low Side
    32. 8.32 Wake-up Times From Low-Power Modes and Reset
    33. 8.33 Timer_A
    34. 8.34 Timer_B
    35. 8.35 USCI (UART Mode) Clock Frequency
    36. 8.36 USCI (UART Mode)
    37. 8.37 USCI (SPI Master Mode) Clock Frequency
    38. 8.38 USCI (SPI Master Mode)
    39. 8.39 USCI (SPI Slave Mode)
    40. 8.40 USCI (I2C Mode)
    41. 8.41 10-Bit ADC, Power Supply and Input Range Conditions
    42. 8.42 10-Bit ADC, Timing Parameters
    43. 8.43 10-Bit ADC, Linearity Parameters
    44. 8.44 REF, External Reference
    45. 8.45 REF, Built-In Reference
    46. 8.46 Comparator_B
    47. 8.47 Flash Memory
    48. 8.48 JTAG and Spy-Bi-Wire Interface
    49. 8.49 DVIO BSL Entry
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
      1. 9.5.1 Bootloader – I2C
      2. 9.5.2 Bootloader – UART
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Port Mapping Controller
      3. 9.9.3  Oscillator and System Clock
      4. 9.9.4  Power-Management Module (PMM)
      5. 9.9.5  Hardware Multiplier
      6. 9.9.6  Real-Time Clock (RTC_A)
      7. 9.9.7  Watchdog Timer (WDT_A)
      8. 9.9.8  System Module (SYS)
      9. 9.9.9  DMA Controller
      10. 9.9.10 Universal Serial Communication Interface (USCI)
      11. 9.9.11 TA0
      12. 9.9.12 TA1
      13. 9.9.13 TA2
      14. 9.9.14 TB0
      15. 9.9.15 Comparator_B
      16. 9.9.16 ADC10_A
      17. 9.9.17 CRC16
      18. 9.9.18 Reference (REF) Module Voltage Reference
      19. 9.9.19 Embedded Emulation Module (EEM) (S Version)
      20. 9.9.20 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
      10. 9.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 9.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  支持资源
    7. 10.7  Trademarks
    8. 10.8  静电放电警告
    9. 10.9  Export Control Notice
    10. 10.10 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

1 特性

  • 双电源电压器件
    • 主电源（AVCC、DVCC）
      • 由外部电源供电：
        从 3.6V 低至 1.8V
      • 多达 18 个通用 I/O，支持多达 8 个外部中断
    • 低压接口电源 (DVIO)
      • 由单独的外部电源供电：1.62 V 至 1.98 V
      • 多达 35 个通用 I/O，支持多达 16 个外部中断
      • 串行通信
  • 超低功耗
    • 工作模式 (AM)：
      所有系统时钟均工作
      在 8MHz、3.0V 且闪存程序执行时为 290µA/MHz（典型值）
      在 8MHz、3.0V 且 RAM 程序执行时为 150µA/MHz（典型值）
    • 待机模式 (LPM3)：
      含晶体的实时时钟 (RTC)、看门狗、电源监控器可用，完全 RAM 保持，快速唤醒：
      2.2V 时为 2.1µA，3.0V 时为 2.3µA（典型值）
      低功耗振荡器 (VLO)、通用计数器、看门狗、电源监控器可用，完全 RAM 保持，快速唤醒：
      3.0V 时为 1.6µA（典型值）
    • 关闭模式 (LPM4)：
      完全 RAM 保持、电源监控器可用、快速唤醒：
      3.0V 时为 1.3µA（典型值）
    • 关断模式 (LPM4.5)：
      3.0V 时为 0.18µA（典型值）
  • 在 3.5μs（典型值）内从待机模式唤醒
  • 16 位 RISC 架构，扩展存储器，高达 25MHz 的系统时钟
  • 灵活的电源管理系统
    • 具有可编程稳压内核电源电压的完全集成 LDO
    • 电源电压监控、监视和欠压保护
  • 单一时钟系统
    • 针对频率稳定的锁相环 (FLL) 控制环路
    • 低功耗低频内部时钟源 (VLO)
    • 低频修整内部基准源 (REFO)
    • 32kHz 手表晶振 (XT1)
    • 高达 32MHz 的高频晶体 (XT2)
  • 配有五个捕捉/比较寄存器的 16 位计时器 TA0，Timer_A
  • 配有三个捕捉/比较寄存器的 16 位计时器 TA1，Timer_A
  • 配有三个捕捉/比较寄存器的 16 位计时器 TA2，Timer_A
  • 具有七个捕捉/比较影子寄存器的 16 位计时器 TB0，Timer_B
  • 四个通用串行通信接口
    • USCI_A0、A1、A2 和 A3 均支持：
      • 具有自动波特率检测功能的增强型通用异步收发器 (UART)
      • 红外数据通讯 (IrDA) 编码器和解码器
      • 同步 SPI
    • USCI_B0、B1、B2 和 B3 均支持：
      • I2C
      • 同步串行外设接口 (SPI)
  • 带内部基准、采样保持功能的 10 位模数转换器 (ADC)
  • 比较器
  • 硬件乘法器支持 32 位运算
  • 串行板上编程，无需外部编程电压
  • 3 通道内部 DMA
  • 具有 RTC 功能的基本定时器
  • 器件比较汇总了可用的产品系列成员和封装