1. 特性
  2. 应用
  3. 说明
    1.     降压效率与输出电流的关系
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Step-Down DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
      2. 7.3.2  Boost Converter
      3. 7.3.3  Spread-Spectrum Mode
      4. 7.3.4  Sync Clock Functionality
      5. 7.3.5  Power-Up
      6. 7.3.6  Buck and Boost Control
        1. 7.3.6.1 Enabling and Disabling Converters
        2. 7.3.6.2 Changing Buck Output Voltage
      7. 7.3.7  Enable and Disable Sequences
      8. 7.3.8  Window Watchdog
      9. 7.3.9  Device Reset Scenarios
      10. 7.3.10 Diagnostics and Protection Features
        1. 7.3.10.1 Voltage Monitorings
        2. 7.3.10.2 Interrupts
        3. 7.3.10.3 Power-Good Information to Interrupt and PG0 and PG1 Pins
          1. 7.3.10.3.1 PGx Pin Gated (Unusual) Mode
          2. 7.3.10.3.2 PGx pin Operation in Continuous Mode
          3. 7.3.10.3.3 Summary of PG0, PG1 Gated and Continuous Operating Modes
        4. 7.3.10.4 Warning Interrupts for System Level Diagnostics
          1. 7.3.10.4.1 Output Power Limit
          2. 7.3.10.4.2 Thermal Warning
        5. 7.3.10.5 Protections Causing Converter Disable
          1. 7.3.10.5.1 Short-Circuit and Overload Protection
          2. 7.3.10.5.2 Overvoltage Protection
          3. 7.3.10.5.3 Thermal Shutdown
        6. 7.3.10.6 Protections Causing Device Power Down
          1. 7.3.10.6.1 Undervoltage Lockout
      11. 7.3.11 OTP Error Correction
      12. 7.3.12 Operation of GPO Signals
      13. 7.3.13 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1 LP8770_map Registers
          1. 7.6.1.1.1  DEV_REV Register (Offset = 0h) [reset = 0h]
            1. Table 11. DEV_REV Register Field Descriptions
          2. 7.6.1.1.2  OTP_CODE Register (Offset = 1h) [reset = 0h]
            1. Table 12. OTP_CODE Register Field Descriptions
          3. 7.6.1.1.3  BUCK0_CTRL_1 Register (Offset = 2h) [reset = 8h]
            1. Table 13. BUCK0_CTRL_1 Register Field Descriptions
          4. 7.6.1.1.4  BUCK0_CTRL_2 Register (Offset = 3h) [reset = 1Ah]
            1. Table 14. BUCK0_CTRL_2 Register Field Descriptions
          5. 7.6.1.1.5  BUCK1_CTRL_1 Register (Offset = 4h) [reset = 8h]
            1. Table 15. BUCK1_CTRL_1 Register Field Descriptions
          6. 7.6.1.1.6  BUCK1_CTRL_2 Register (Offset = 5h) [reset = 1Ah]
            1. Table 16. BUCK1_CTRL_2 Register Field Descriptions
          7. 7.6.1.1.7  BUCK0_VOUT Register (Offset = 6h) [reset = 0h]
            1. Table 17. BUCK0_VOUT Register Field Descriptions
          8. 7.6.1.1.8  BUCK1_VOUT Register (Offset = 7h) [reset = 0h]
            1. Table 18. BUCK1_VOUT Register Field Descriptions
          9. 7.6.1.1.9  BOOST_CTRL Register (Offset = 8h) [reset = 8h]
            1. Table 19. BOOST_CTRL Register Field Descriptions
          10. 7.6.1.1.10 BUCK0_DELAY Register (Offset = 9h) [reset = 0h]
            1. Table 20. BUCK0_DELAY Register Field Descriptions
          11. 7.6.1.1.11 BUCK1_DELAY Register (Offset = Ah) [reset = 0h]
            1. Table 21. BUCK1_DELAY Register Field Descriptions
          12. 7.6.1.1.12 BOOST_DELAY Register (Offset = Bh) [reset = 0h]
            1. Table 22. BOOST_DELAY Register Field Descriptions
          13. 7.6.1.1.13 GPO0_DELAY Register (Offset = Ch) [reset = 0h]
            1. Table 23. GPO0_DELAY Register Field Descriptions
          14. 7.6.1.1.14 GPO1_DELAY Register (Offset = Dh) [reset = 0h]
            1. Table 24. GPO1_DELAY Register Field Descriptions
          15. 7.6.1.1.15 GPO2_DELAY Register (Offset = Eh) [reset = 0h]
            1. Table 25. GPO2_DELAY Register Field Descriptions
          16. 7.6.1.1.16 GPO_CONTROL_1 Register (Offset = Fh) [reset = AAh]
            1. Table 26. GPO_CONTROL_1 Register Field Descriptions
          17. 7.6.1.1.17 GPO_CONTROL_2 Register (Offset = 10h) [reset = Ah]
            1. Table 27. GPO_CONTROL_2 Register Field Descriptions
          18. 7.6.1.1.18 CONFIG Register (Offset = 11h) [reset = 3Ch]
            1. Table 28. CONFIG Register Field Descriptions
          19. 7.6.1.1.19 PLL_CTRL Register (Offset = 12h) [reset = 2h]
            1. Table 29. PLL_CTRL Register Field Descriptions
          20. 7.6.1.1.20 PGOOD_CTRL Register (Offset = 13h) [reset = 0h]
            1. Table 30. PGOOD_CTRL Register Field Descriptions
          21. 7.6.1.1.21 PGOOD_LEVEL_1 Register (Offset = 14h) [reset = 0h]
            1. Table 31. PGOOD_LEVEL_1 Register Field Descriptions
          22. 7.6.1.1.22 PGOOD_LEVEL_2 Register (Offset = 15h) [reset = 0h]
            1. Table 32. PGOOD_LEVEL_2 Register Field Descriptions
          23. 7.6.1.1.23 PGOOD_LEVEL_3 Register (Offset = 16h) [reset = 0h]
            1. Table 33. PGOOD_LEVEL_3 Register Field Descriptions
          24. 7.6.1.1.24 PG_CTRL Register (Offset = 17h) [reset = 2h]
            1. Table 34. PG_CTRL Register Field Descriptions
          25. 7.6.1.1.25 PG0_CTRL Register (Offset = 18h) [reset = 0h]
            1. Table 35. PG0_CTRL Register Field Descriptions
          26. 7.6.1.1.26 PG0_FAULT Register (Offset = 19h) [reset = 0h]
            1. Table 36. PG0_FAULT Register Field Descriptions
          27. 7.6.1.1.27 PG1_CTRL Register (Offset = 1Ah) [reset = 0h]
            1. Table 37. PG1_CTRL Register Field Descriptions
          28. 7.6.1.1.28 PG1_FAULT Register (Offset = 1Bh) [reset = 0h]
            1. Table 38. PG1_FAULT Register Field Descriptions
          29. 7.6.1.1.29 WD_CTRL_1 Register (Offset = 1Ch) [reset = 0h]
            1. Table 39. WD_CTRL_1 Register Field Descriptions
          30. 7.6.1.1.30 WD_CTRL_2 Register (Offset = 1Dh) [reset = 1h]
            1. Table 40. WD_CTRL_2 Register Field Descriptions
          31. 7.6.1.1.31 WD_STATUS Register (Offset = 1Eh) [reset = 0h]
            1. Table 41. WD_STATUS Register Field Descriptions
          32. 7.6.1.1.32 RESET Register (Offset = 1Fh) [reset = 0h]
            1. Table 42. RESET Register Field Descriptions
          33. 7.6.1.1.33 INT_TOP_1 Register (Offset = 20h) [reset = 0h]
            1. Table 43. INT_TOP_1 Register Field Descriptions
          34. 7.6.1.1.34 INT_TOP_2 Register (Offset = 21h) [reset = 0h]
            1. Table 44. INT_TOP_2 Register Field Descriptions
          35. 7.6.1.1.35 INT_BUCK Register (Offset = 22h) [reset = 0h]
            1. Table 45. INT_BUCK Register Field Descriptions
          36. 7.6.1.1.36 INT_BOOST Register (Offset = 23h) [reset = 0h]
            1. Table 46. INT_BOOST Register Field Descriptions
          37. 7.6.1.1.37 INT_DIAG Register (Offset = 24h) [reset = 0h]
            1. Table 47. INT_DIAG Register Field Descriptions
          38. 7.6.1.1.38 TOP_STATUS Register (Offset = 25h) [reset = 0h]
            1. Table 48. TOP_STATUS Register Field Descriptions
          39. 7.6.1.1.39 BUCK_STATUS Register (Offset = 26h) [reset = 0h]
            1. Table 49. BUCK_STATUS Register Field Descriptions
          40. 7.6.1.1.40 BOOST_STATUS Register (Offset = 27h) [reset = 0h]
            1. Table 50. BOOST_STATUS Register Field Descriptions
          41. 7.6.1.1.41 DIAG_STATUS Register (Offset = 28h) [reset = 0h]
            1. Table 51. DIAG_STATUS Register Field Descriptions
          42. 7.6.1.1.42 TOP_MASK_1 Register (Offset = 29h) [reset = 0h]
            1. Table 52. TOP_MASK_1 Register Field Descriptions
          43. 7.6.1.1.43 TOP_MASK_2 Register (Offset = 2Ah) [reset = 1h]
            1. Table 53. TOP_MASK_2 Register Field Descriptions
          44. 7.6.1.1.44 BUCK_MASK Register (Offset = 2Bh) [reset = 0h]
            1. Table 54. BUCK_MASK Register Field Descriptions
          45. 7.6.1.1.45 BOOST_MASK Register (Offset = 2Ch) [reset = 0h]
            1. Table 55. BOOST_MASK Register Field Descriptions
          46. 7.6.1.1.46 DIAG_MASK Register (Offset = 2Dh) [reset = 0h]
            1. Table 56. DIAG_MASK Register Field Descriptions
          47. 7.6.1.1.47 SEL_I_LOAD Register (Offset = 2Eh) [reset = 0h]
            1. Table 57. SEL_I_LOAD Register Field Descriptions
          48. 7.6.1.1.48 I_LOAD_2 Register (Offset = 2Fh) [reset = 0h]
            1. Table 58. I_LOAD_2 Register Field Descriptions
          49. 7.6.1.1.49 I_LOAD_1 Register (Offset = 30h) [reset = 0h]
            1. Table 59. I_LOAD_1 Register Field Descriptions
          50. 7.6.1.1.50 FREQ_SEL Register (Offset = 31h) [reset = 0h]
            1. Table 60. FREQ_SEL Register Field Descriptions
          51. 7.6.1.1.51 BOOST_ILIM_CTRL Register (Offset = 32h) [reset = 0h]
            1. Table 61. BOOST_ILIM_CTRL Register Field Descriptions
          52. 7.6.1.1.52 ECC_STATUS Register (Offset = 33h) [reset = 0h]
            1. Table 62. ECC_STATUS Register Field Descriptions
          53. 7.6.1.1.53 WD_DIS_CTRL_CODE Register (Offset = 34h) [reset = 0h]
            1. Table 63. WD_DIS_CTRL_CODE Register Field Descriptions
          54. 7.6.1.1.54 WD_DIS_CONTROL Register (Offset = 35h) [reset = 0h]
            1. Table 64. WD_DIS_CONTROL Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Application Components
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Buck Input Capacitor Selection
          3. 8.2.2.1.3 Buck Output Capacitor Selection
          4. 8.2.2.1.4 Boost Input Capacitor Selection
          5. 8.2.2.1.5 Boost Output Capacitor Selection
          6. 8.2.2.1.6 Supply Filtering Components
      3. 8.2.3 Current Limit vs Maximum Output Current
      4. 8.2.4 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息