ZHCSGU2A 数据表 | 德州仪器 TI.com.cn

ZHCSGU2A July 2017 – September 2017 LP5569

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

RTW|24
- MPQF167C

散热焊盘机械数据 (封装 | 引脚)

RTW|24
- QFND062N

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7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
Voltage on VIN, CLK, ADDR, EN/PWM, GPIO/TRIG/INT, SCL, SDA, VOUT⁽²⁾	–0.3	6	V
Voltage on LED0 to LED8, C1–, C2–, C1+, C2+	−0.3	V_VIN + 0.3 V with 6 V max.	V
Voltage on V1P8	−0.3	2	V
Continuous power dissipation	Internally limited	Internally limited
Junction temperature, T_J-MAX	–40	125	°C
Storage temperature, T_stg	−65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) VOUT cannot be forced to a power supply during device shutdown.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Input voltage on VIN	2.5	5.5	V
Voltage on LED0 to LED8, C1–, C2–, C1+, C2+, VOUT	0	V_VIN	V
Voltage on CLK, ADDR, EN/PWM, GPIO/TRIG/INT, SDA, SCL	0	V_VIN	V
Input voltage on V1P8	1.65	1.95	V
Output current on VOUT	0	160	mA
Operating ambient temperature, T_A ⁽¹⁾	−40	85	°C

(1) In applications where high power dissipation and/or poor PCB cooling status is present, the maximum ambient temperature might require derating. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP= 125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the device in the application (R_θJA), as given by the equation: T_A-MAX = T_J-MAX-OP – (R_θJA × P_D-MAX).

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP5569	UNIT
		RTW (WQFN)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	35.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	26.7	°C/W
R_θJB	Junction-to-board thermal resistance	13.1	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	13.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4.6	°C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

7.5 Electrical Characteristics

Unless otherwise noted, specifications apply to the LP5569 device in a circuit per the typical application diagram for the single device with V_VIN = 3.6 V, V1P8 = 1.8 V, V_EN/PWM = V_VIN, C_IN = C_OUT= C_FLY1 = C_FLY2 = 1 µF. Typical (TYP) values apply for T_A = 25°C and minimum (MIN) and maximum (MAX) apply over the operating ambient temperature range (−40°C < T_A < 85°C).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_VIN	Standby supply current	V_EN/PWM = 0 V, chip_en (bit) = 0		0.2	1	µA
		V_EN/PWM = 3.3 V, chip_en (bit) = 0, external CLK not running		1	2
		V_EN/PWM = 3.3 V, chip_en (bit) = 0, external CLK running		2	4
	Normal-mode supply current	External CLK running, charge pump and current sinks disabled		56	70	µA
		Charge pump in 1× mode, no load, current sinks disabled		65	90	µA
		Charge pump in 1.5× mode, no load, current-sink outputs disabled		1.8		mA
	Power-save mode supply current	External CLK running, see Automatic Power-Save Mode		10	15	µA
	Power-save mode supply current	Internal oscillator running		10	15	µA
I_V1P8	Standby supply current	V_EN/PWM = 0 V, chip_en(bit) = 0		0.2	1	µA
		V_EN/PWM = 3.3 V, chip_en (bit) = 0, external CLK not running		0.2	2	µA
		V_EN/PWM = 3.3 V, chip_en (bit) = 0, external CLK running		1	4	µA
	Normal-mode supply current	External CLK running, charge pump and current sinks disabled		174	190	µA
		Charge pump in 1× mode, no load, current sinks disabled		174	190	µA
		Charge pump in 1.5× mode, no load, current-sink- outputs disabled		180		µA
	Powersave-mode supply current	External CLK running		1	5	µA
	Powersave-mode supply current	Internal oscillator running		1	5	µA
ƒ_OSC	32-kHz internal oscillator frequency accuracy	T_A = 25°C	–10%		10%
ƒ_OSC	10-MHz internal oscillator frequency accuracy		–7%		7%
V_UVLO	Undervoltage lockout	V_VIN falling		2.2		V
V_UVLO	Undervoltage lockout	V_VIN rising		2.3		V

7.6 Charge-Pump Electrical Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
R_OUT	Charge-pump output resistance	Gain = 1×, V_VIN= 4.2 V		1		Ω
R_OUT	Charge-pump output resistance	Gain = 1.5×, V_VIN = 3.7 V		3.5		Ω
V_OUT		V_VIN = 3.7 V, I_OUT = 160 mA, gain = 1.5×	4.41	4.5	4.59	V
ƒ_SW	Switching frequency			1.25		MHz
I_CL	Output current limit	V_OUT = 0 V, V_VIN = 3.7 V, CP_CONFIG = 0xFF		600		mA
t_ON	V_OUT turnon time	I_OUT = 0 mA, V_IN ≥ 3 V, V_OUT > 4.1 V, gain = 1.5×		100		µs
I_OUT	Maximum output current	V_VIN > 3.1 V, V_OUT dropped 10%, gain = 1.5×		200		mA
I_OUT	Maximum output current	V_IN > 2.5 V, V_OUT dropped 10%, gain = 1.5×		150		mA

7.7 LED Current Sinks Electrical Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_LEAKAGE	Leakage current (LED0 to LED8)	PWM = 0%, V_LED = 5 V			1	µA
I_MAX	Maximum sink current		24.5	25.5	26.5	mA
I_{LED_ACC}	Sink current accuracy⁽¹⁾	Current set to 17.5 mA. PWM = 100%	–4.5%		4.5%
I_{LED_MATCH}	Matching⁽¹⁾	Current set to 17.5 mA		1%	2.5%
ƒ_LED	LED switching frequency			19.5		kHz
V_SAT	Saturation voltage⁽²⁾	Output current set to 25.5 mA		90	110	mV

(1) Output-current accuracy is the difference between the actual value of the output current and the programmed value of this current. Matching is the maximum difference from the average. For the constant-current outputs on the device (LED0 to LED8), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). The matching number is calculated: (MAX – MIN) / AVG. The typical specification provided is the most likely norm of the matching figure for all devices. Note that some manufacturers have different definitions in use.

(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.

7.8 Logic Interface Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
LOGIC INPUT (EN/PWM, SCL, ADDR)
V_IL	Input low level				0.4	V
V_IH	Input high level		1.25			V
I_lkg	Input leakage current	V_I ≤ V_VIN	–1		1	µA
LOGIC OUTPUT (SDA, GPIO/TRIG/INT, CLK)
V_IL	Input low level	Pin configured as input			0.4	V
V_IH	Input high level	Pin configured as input	1.25			V
I_lkg	Input leakage current	Pin configured as input, V_VIN = 5.5 V, V_I≤ V_VIN	–1		1	µA
V_OL	Output low level	I_PULLUP = 3 mA		0.2	0.5	V
I_L	Output leakage current	Pin configured as output, Hi-Z state			1	µA

7.9 Timing Requirements (EN/PWM)

		TYP	MAX	UNIT
t_EN	Enable time, EN/PWM first rising edge until first I²C access	2	3	ms
t_{EN_TIMEOUT}	EN timeout, EN/PWM = low time while in standby mode (enable function)	15		ms
t_{PWM_TIMEOUT}	PWM timeout, EN/PWM = low time while in normal mode (PWM function)	15		ms
PWM_res	Resolution for EN/PWM input when configured as PWM, f_PWM=10 kHz	10		bits

7.10 Serial-Bus Timing Requirements (SDA, SCL), See Figure 1

I²C fast mode

		MIN	MAX	UNIT
ƒ_SCL	Clock frequency	0	400	kHz
1	Hold time (repeated) START condition	0.6		µs
2	Clock low time	1.3		µs
3	Clock high time	600		ns
4	Setup time for a repeated START condition	600		ns
5	Data hold time	0		ns
6	Data setup time	100		ns
7	Rise time of SDA and SCL	20 + 0.1Cb	300	ns
8	Fall time of SDA and SCL	15 + 0.1Cb	300	ns
9	Setup time for STOP condition	600		ns
10	Bus-free time between a STOP and a START condition	1.3		µs
Cb	Capacitive load for each bus line	10	200	pF

7.11 External Clock Timing Requirements (CLK), See Figure 2

over operating ambient temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
ƒ_CLK	Clock frequency		32.7		kHz
t_CLKH	High time	6			µs
t_CLKL	Low time	6			µs
t_r	Clock rise time, 10% rising edge to 90% rising edge			2	µs
t_f	Clock fall time, 90% falling edge to 10% falling edge			2	µs

Figure 1. Timing Parameters

Figure 2. External Clock Signal

7.12 Typical Characteristics

Unless otherwise specified: V_VIN = 3.6 V, C_IN = C_OUT = 1 μF, C1 = C2 = 1 μF, T_A = 25°C. C_IN, C_OUT, C1, C2: Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.