SNVSAA7A December   2015  – May 2016 LM53625-Q1 , LM53635-Q1


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Circuit
      2.      Typical Automotive Layout (22 mm x 12.5 mm)
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Input Voltage Frequency Foldback
    5. 8.5 Spread-Spectrum Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. External Components Selection
            1. Input Capacitors
              1. Input Capacitor Selection
            2. Output Inductors and Capacitors Selection
              1. Inductor Selection
              2. Output Capacitor Selection
          2. Setting the Output Voltage
            1. FB for Adjustable Versions
          3. VCC
          4. BIAS
          5. CBOOT
          6. Maximum Ambient Temperature
        3. Application Curves
      2. 9.2.2 Fixed 5-V Output for USB-Type Applications
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 9.2.3 Fixed 3.3-V Output
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      4. 9.2.4 Adjustable Output
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
    3. 9.3 Do's and Don't's
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information


请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RNL|22
散热焊盘机械数据 (封装 | 引脚)


With a logic high on the FPWM input, the device is locked in PWM mode. This operation is maintained, even at no-load, by allowing the inductor current to reverse its normal direction. This mode trades off reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching frequency. In this mode, a negative current limit of INEG is imposed to prevent damage to the low-side FET of the regulator. When in FPWM the converter synchronizes to any valid clock signal on the SYNC input (see Dropout andInput Voltage Frequency Foldback.

When constant frequency operation is more important than light load efficiency, pull the LM53625/35-Q1 FPWM input high or provide a valid synchronization input. Once activated, this feature ensures that the switching frequency stays above the AM frequency band, while operating between the minimum and maximum duty cycle limits. Essentially, the diode emulation feature is turned off in this mode. This means that the device remains in CCM under light loads. Under conditions where the device must reduce the on time or off time below the ensured minimum, the frequency reduces to maintain the effective duty cycle required for regulation. This can occur for high input/output voltage ratios.

With the FPWM pin pulled low (normal mode), the diode emulation feature is activated. Device operation is the same as above; however, the regulator goes into DCM operation when the valley of the inductor current reaches zero.

This feature may be activated and deactivated while the part is regulating without removing the load. This feature activates and deactivates gradually, over approximately 40 µs, preventing perturbation of output voltage. When in FPWM mode, a limited reverse current is allowed through the inductor allowing power to pass from the regulators output to its input. In this case, care must be taken to ensure that a large enough input capacitor is used to absorb this reverse current.


While FPWM is activated, larger currents pass through the inductor than in AUTO mode when lightly loaded. This may result in more EMI, though at a predictable frequency. Once loads are heavy enough to necessitate CCM operation, FPWM has no measurable effect on the operation of the regulator.