SNVS265C December   2003  – January 2016 LM5025

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High-Voltage Start-Up Regulator
      2. 7.3.2  Line Undervoltage Detector
      3. 7.3.3  PWM Outputs
      4. 7.3.4  Compound Gate Drivers
      5. 7.3.5  PWM Comparator
      6. 7.3.6  Volt Second Clamp
      7. 7.3.7  Current Limit
      8. 7.3.8  Oscillator and Sync Capability
      9. 7.3.9  Feed-Forward Ramp
      10. 7.3.10 Soft-Start
      11. 7.3.11 Thermal Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Oscillator
        2. 8.2.2.2 Soft-Start Ramp Time and Hiccup Interval
        3. 8.2.2.3 Feed-Forward Ramp and Maximum On Time Clamp
        4. 8.2.2.4 Dead Times
      3. 8.2.3 Application Curves
      4. 8.2.4 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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1 Features

  • Internal Start-Up Bias Regulator
  • 3-A Compound Main Gate Driver
  • Programmable Line Undervoltage Lockout (UVLO) With Adjustable Hysteresis
  • Voltage Mode Control With Feed-Forward
  • Adjustable Dual-Mode Overcurrent Protection
  • Programmable Overlap or Deadtime Between the Main and Active Clamp Outputs
  • Volt × Second Clamp
  • Programmable Soft-Start
  • Leading Edge Blanking
  • Single Resistor Programmable Oscillator
  • Oscillator UP and DOWN Sync Capability
  • Precision 5-V Reference
  • Thermal Shutdown

2 Applications

  • Server Power Supplies
  • 48-V Telecom Power Supplies
  • 42-V Automotive Applications
  • High-Efficiency DC-to-DC Power Supplies

3 Description

The LM5025 PWM controller contains all of the features necessary to implement power converters using the active clamp and reset technique. The device can be configured to control either a
P-channel clamp switch or an N-channel clamp switch. With the active clamp technique, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp and reset techniques.

Two control outputs are provided, the main power switch control (OUT_A), and the active clamp switch control (OUT_B). The active clamp output can be configured for either a specified overlap time
(for P-channel switch applications) or a specified deadtime (for N_channel applications). The two internal compound gate drivers parallel both MOS and bipolar devices, providing superior gate drive characteristics. This controller is designed for high-speed operation including an oscillator frequency range up to 1 MHz and total PWM and current sense propagation delays less than 100 ns.

The LM5025 includes a high-voltage start-up regulator that operates over a wide input range of
13 V to 90 V. Additional features include: line undervoltage lockout (UVLO), soft-start, oscillator UP and DOWN sync capability, precision reference and thermal shutdown.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM5025 TSSOP (16) 5.00 mm × 4.40 mm
WSON (16) 5 00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

LM5025 20086901.gif