ZHCSEN9A NOVEMBER   2014  – January 2016 DS90UB940-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 应用 图
  5. 5 修订历史记录
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings—JEDEC
    3. 7.3  ESD Ratings—IEC and ISO
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  DC Electrical Characteristics
    7. 7.7  AC Electrical Characteristics
    8. 7.8  Timing Requirements for the Serial Control Bus
    9. 7.9  Switching Characteristics
    10. 7.10 Timing Diagrams and Test Circuits
    11. 7.11 Power Sequence
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High Speed Forward Channel Data Transfer
      2. 8.3.2  Low Speed Back Channel Data Transfer
      3. 8.3.3  FPD-Link III Port Register Access
      4. 8.3.4  Clock and Output Status
      5. 8.3.5  LVCMOS VDDIO Option
      6. 8.3.6  Power Down (PDB)
      7. 8.3.7  Interrupt Pin — Functional Description and Usage (INTB_IN)
      8. 8.3.8  General-purpose I/O
        1. 8.3.8.1 GPIO[3:0] and D_GPIO[3:0] Configuration
        2. 8.3.8.2 Back Channel Configuration
        3. 8.3.8.3 GPIO_REG[8:5] Configuration
      9. 8.3.9  SPI Communication
        1. 8.3.9.1 SPI Mode Configuration
        2. 8.3.9.2 Forward Channel SPI Operation
        3. 8.3.9.3 Reverse Channel SPI Operation
      10. 8.3.10 Backward Compatibility
      11. 8.3.11 Input Equalization
      12. 8.3.12 I2S Audio Interface
        1. 8.3.12.1 I2S Transport Modes
        2. 8.3.12.2 I2S Jitter Cleaning
        3. 8.3.12.3 MCLK
      13. 8.3.13 Built-In Self Test (BIST)
        1. 8.3.13.1 BIST Configuration And Status
          1. 8.3.13.1.1 Sample BIST Sequence
        2. 8.3.13.2 Forward Channel and Back Channel Error Checking
      14. 8.3.14 Internal Pattern Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Configuration Select
        1. 8.4.1.1 1-lane FPD-Link III Input, 4 MIPI lanes Output
        2. 8.4.1.2 1-lane FPD-Link III Input, 2 MIPI lanes Output
        3. 8.4.1.3 2-lane FPD-Link III Input, 4 MIPI lanes Output
        4. 8.4.1.4 2-lane FPD-Link III Input, 2 MIPI lanes Output
        5. 8.4.1.5 1- or 2-lane FPD-Link III Input, 2 or 4 MIPI lanes Output in Replicate
      2. 8.4.2 MODE_SEL[1:0]
      3. 8.4.3 CSI-2 Interface
      4. 8.4.4 Input Display Timing
      5. 8.4.5 MIPI CSI-2 Output Data Formats
      6. 8.4.6 Non-Continuous / Continuous Clock
      7. 8.4.7 Ultra Low Power State (ULPS)
      8. 8.4.8 CSI-2 Data Identifier
    5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
      2. 8.5.2 Multi-Master Arbitration Support
      3. 8.5.3 I2C Restrictions on Multi-Master Operation
      4. 8.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices
      5. 8.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices
      6. 8.5.6 Restrictions on Control Channel Direction for Multi-Master Operation
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 PCB Layout and Power System Considerations
        2. 9.2.2.2 CML Interconnect Guidelines
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
    1. 10.1 Power Up Requirements and PDB Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Power Supply Recommendations

This device provides separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description table provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.

10.1 Power Up Requirements and PDB Pin

When power is applied, power from the highest voltage rail to the lowest voltage rail on any of the supply pins. For 3.3V IO operation, VDDIO and VDD33 can be powered by the same supply and ramped simultaneously. The power supply ramp (VDD12, VDD33, and VDDIO) should be faster than 1.5ms with a monotonic rise. A large capacitor on the PDB pin is needed to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDD33, a 10 kΩ pull-up and a >10 μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until both VDD33 and VDDIO has reached steady state. Pins VDD33_A and VDD33_B should both be externally connected, bypassed, and driven to the same potential (they are not internally connected).