ZHCSEC0A January   2013  – October 2015 DS100RT410

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Data Path Operation
      2. 7.3.2  Signal Detect
      3. 7.3.3  CTLE
      4. 7.3.4  Clock and Data Recovery
      5. 7.3.5  Output Driver
      6. 7.3.6  CTLE Boost Setting
      7. 7.3.7  Driver Output Voltage
      8. 7.3.8  Driver Output De-Emphasis
      9. 7.3.9  Driver Output Rise and Fall Time
      10. 7.3.10 Ref_mode 0 Mode (Reference Clock Not Required)
      11. 7.3.11 Ref_mode 3 Mode (Reference Clock Required)
      12. 7.3.12 False Lock Detector Setting
      13. 7.3.13 Reference Clock In
      14. 7.3.14 Reference Clock Out
      15. 7.3.15 Daisy Chain of REFCLK_OUT to REFCLK_IN
      16. 7.3.16 INT
      17. 7.3.17 LOCK_3, LOCK_2, LOCK_1, and LOCK_0
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode and SMBus Slave Mode
      2. 7.4.2 Address Lines <ADDR_[3:0]>
      3. 7.4.3 SDA and SDC
    5. 7.5 Programming
      1. 7.5.1  SMBus Strap Observation
      2. 7.5.2  Device Revision and Device ID
      3. 7.5.3  Control/Shared Register Reset
      4. 7.5.4  Interrupt Channel Flag Bits
      5. 7.5.5  SMBus Master Mode Control Bits
      6. 7.5.6  Resetting Individual Channels of the Retimer
      7. 7.5.7  Interrupt Status
      8. 7.5.8  Overriding the CTLE Boost Setting
      9. 7.5.9  Overriding the VCO CAP DAC Values
      10. 7.5.10 Overriding the Output Multiplexer
      11. 7.5.11 Overriding the VCO Divider Selection
      12. 7.5.12 Using the PRBS Generator
      13. 7.5.13 Using the Internal Eye Opening Monitor
      14. 7.5.14 Enabling Slow Rise and Fall Time on the Output Driver
      15. 7.5.15 Inverting the Output Polarity
      16. 7.5.16 Overriding the Figure of Merit for Adaptation
      17. 7.5.17 Setting the Rate and Subrate for Lock Acquisition
      18. 7.5.18 Setting the Adaptation/Lock Mode
      19. 7.5.19 Initiating Adaptation
      20. 7.5.20 Setting the Reference Enable Mode
      21. 7.5.21 Overriding the CTLE Settings Used for CTLE Adaptation
      22. 7.5.22 Setting the Output Differential Voltage
      23. 7.5.23 Setting the Output De-emphasis Setting
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
      2. 7.6.2 Bit Fields in the Register Set
      3. 7.6.3 Writing to and Reading from the Control/Shared Registers
      4. 7.6.4 Channel Select Register
      5. 7.6.5 Reading to and Writing from the Channel Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

RHS Package
48 Pin WQFN
Top View
DS100RT410 30160826.gif

Pin Functions

PIN I/O, TYPE(1) DESCRIPTION
NAME NO.
HIGH-SPEED DIFFERENTIAL I/O
RXP0
RXN0		 1
2		 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100 Ω. Must be AC coupled.
RXP1
RXN1		 4
5		 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100 Ω. Must be AC coupled.
RXP2
RXN2		 8
9		 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100 Ω. Must be AC coupled.
RXP3
RXN3		 11
12		 I, CML Inverting and non-inverting CML-compatible differential inputs to the equalizer. Nominal differential input impedance = 100 Ω. Must be AC coupled.
TXP0
TXN0		 36
35		 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100 Ω. Must be AC coupled.
TXP1
TXN1		 33
32		 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100 Ω. Must be AC coupled.
TXP2
TXN2		 29
28		 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100 Ω. Must be AC coupled.
TXP3
TXN3		 26
25		 O, CML Inverting and non-inverting CML-compatible differential outputs from the driver. Nominal differential output impedance = 100 Ω. Must be AC coupled.
LOOP FILTER CONNECTION PINS
LPF_CP_0
LPF_REF_0		 47
48		 I/O, analog Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_0 and LPF_REF_0
LPF_CP_1
LPF_REF_1		 38
37		 I/O, analog Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_1 and LPF_REF_1
LPF_CP_2
LPF_REF_2		 23
24		 I/O, analog Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_2 and LPF_REF_2
LPF_CP_3
LPF_REF_3		 14
13		 I/O, analog Loop filter connection
Place a 22 nF ± 10% capacitor between LPF_CP_3 and LPF_REF_3
REFERENCE CLOCK I/O
REFCLK_IN 19 I, 2.5-V analog Input is 2.5 V, 25 MHz ± 100-ppm reference clock from external oscillator.
No stringent phase noise requirement
REFCLK_OUT 42 O, 2.5-V analog Output is 2.5 V, buffered replica of reference clock input for connecting multiple DS100RT410 devices on a board
LOCK INDICATOR PINS
LOCK_0
LOCK_1
LOCK_2
LOCK_3		 45
40
21
16		 O, 2.5-V LVCMOS Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding channel.
These pins are shared with SMBus address strap input functions read at start-up.
SMBus MASTER MODE PINS
ALL_DONE 41 O, 2.5-V LVCMOS Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROM read has been completed.
READ_EN 44 I, 2.5-V LVCMOS Input is 2.5 V, a transition from high to low starts the load from the external EEPROM. The READ_EN pin must be tied low when in SMBus slave mode
INTERRUPT OUTPUT
INT 43 O, 3.3-V LVCMOS, Open Drain Used to signal horizontal or vertical eye opening out of tolerance, loss of signal detect, or CDR unlock
External 2-kΩ to 5-kΩ pullup resistor is required.
Pin is 3.3-V LVCMOS tolerant.
SERIAL MANAGEMENT BUS (SMBus) INTERFACE
ADDR_0
ADDR_1
ADDR_2
ADDR_3		 45
40
21
16		 I, 2.5-V LVCMOS Input is 2.5 V, the ADDR_[3:0] pins set the SMBus address for the retimer.
These pins are strap inputs. Their state is read on power-up to set the SMBus address in SMBus control mode.
High = 1-kΩ to VDD, Low = 1-kΩ to GND
These pins are shared with the lock indicator functions. See Table 2.
EN_SMB 20 I, 2.5-V analog Input is 2.5 V, selects SMBus master mode or SMBus slave mode
EN_SMB = High for slave mode
EN_SMB = Float for master mode
Tie READ_EN pin low for SMBus slave mode. See Table 1.
SDA 18 I/O, 3.3-V LVCMOS, Open Drain Data Input and Open Drain Output
External 2-kΩ to 5-kΩ pullup resistor is required.
Pin is 3.3-V LVCMOS tolerant.
SDC 17 I/O, 3.3-V LVCMOS, Open Drain Clock Input / Open Drain Clock Output
External 2-kΩ to 5-kΩ pullup resistor is required.
Pin is 3.3-V LVCMOS tolerant.
POWER
VDD 3, 6, 7,
10, 15, 46		 Power VDD = 2.5 V ± 5%
GND 22, 27,
30, 31,
34, 39		 Power Ground reference.
DAP PAD Power Ground reference. The exposed pad at the center of the package must be connected to ground plane of the board with at least 4 vias to lower the ground impedance and improve the thermal performance of the package.
(1) Notes: I = Input, O = Output and 2.5-V LVCMOS pins are 2.5-V levels only.
Only SMBus pins SDA and SDC and INT pin are 3.3-V tolerant. These three pins are open-drain and require external pullup resistors.