SLVSB17D March   2012  – April 2016 DRV8836

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sleep Mode
      2. 7.3.2 Power Supplies and Input Pins
      3. 7.3.3 Protection Circuits
        1. 7.3.3.1 Overcurrent Protection (OCP)
        2. 7.3.3.2 Thermal Shutdown (TSD)
        3. 7.3.3.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bridge Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Low-Power Operation
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
      2. 10.3.2 Heatsinking
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

The VCC pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1-μF rated for VCC. This capacitor should be placed as close to the VCC pin as possible with a thick trace or ground plane connection to the device GND pin.

The VCC pin must bypass to ground using an appropriate bulk capacitor. This component may be an electrolytic and should be located close to the DRV8836.

10.2 Layout Example

DRV8836 layout_ex_slvsb17.gif Figure 8. Layout Recommendation

10.3 Thermal Considerations

The DRV8836 has thermal shutdown (TSD) as described in Thermal Shutdown (TSD). If the die temperature exceeds approximately 150°C, the device disables until the temperature drops to a safe level.

Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or an ambient temperature that is too high.

10.3.1 Power Dissipation

The power dissipated in the output FET resistance or RDS(on) dominates the power dissipation in the DRV8836. The average power dissipation when running both H-bridges can be roughly estimated by Equation 1:

Equation 1. PTOT = 2 × RDS(ON) × (IOUT(RMS))2

where

  • PTOT is the total power dissipation, RDS(ON) is the resistance of the HS plus LS FETs, and IOUT(RMS) is the RMS output current being applied to each winding. IOUT(RMS) is equal to approximately 0.7× the full-scale output current setting. The factor of 2 comes from the fact that there are two H-bridges.

The maximum amount of power dissipated in the device is dependent on ambient temperature and heatsinking.

NOTE

RDS(ON) increases with temperature. As the device heats, the power dissipation increases. This must be taken into consideration when sizing the heatsink.

10.3.2 Heatsinking

The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers.

For more information on PCB design, refer to TI application report SLMA002, PowerPAD™ Thermally Enhanced Package, and TI application brief SLMA004, PowerPAD™ Made Easy, available at www.ti.com.

In general, the more copper area that can be provided, the more power can be dissipated.