ZHCSA88E August   2012  – December 2018 DLPR410

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     简化应用
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Supply Voltage Requirements for Power-On Reset and Power-Down
    7. 6.7 Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Data Interface
        1. 7.3.1.1 Data Outputs
        2. 7.3.1.2 Configuration Clock Input
        3. 7.3.1.3 Output Enable and Reset
        4. 7.3.1.4 Chip Enable
        5. 7.3.1.5 Configuration Pulse
        6. 7.3.1.6 Revision Selection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件兼容性
      2. 11.1.2 器件命名规则
      3. 11.1.3 器件标记
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Pin Configuration and Functions

YVA Package
48-Pin DSBGA
Top View
DLPR410 po_DLPS065.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
GND A1 G Ground
GND A2 G Ground
OE/RESET A3 I/O Output Enable/RESET (Open-Drain I/O). When Low, this input holds the address counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM completes the internal power-on reset sequence. Polarity is not programmable. Pin must be pulled High using an external 4.7-kΩ pull-up to VCCO.
DNC1 A4 Do Not Connect. Leave unconnected.
D6 A5 Do Not Connect. Leave unconnected.
D7 A6 Do Not Connect. Leave unconnected.
VCCINT1 B1 P Positive 1.8-V supply voltage for internal logic.
VCCO1 B2 P Positive 2.5-V supply voltage connected to the output voltage drivers and internal buffers.
CLK B3 I Do Not Connect. Leave unconnected.
CE B4 I Chip Enable Input. When CE is High, the device is put into low-power standby mode, the address counter is reset, and the DATA and CLKOUT outputs are placed in a high impedance state.
D5 B5 Do Not Connect. Leave unconnected.
GND B6 G Ground
BUSY C1 Do Not Connect. Leave unconnected.
CLKOUT C2 Configuration clock output. Each rising edge on the CLK input increments the internal address counter. Pin must be pulled High and Low using an external 100-Ω pull-up to VCCO and an external 100-Ω pull-down to Ground. Place resistors close to pin.
DNC2 C3 Do Not Connect. Leave unconnected.
DNC3 C4 Do Not Connect. Leave unconnected.
D4 C5 Do Not Connect. Leave unconnected.
VCCO2 C6 P Positive 2.5-V supply voltage connected to the output voltage drivers and internal buffers.
CF D1 I Configuration pin. The CF pin must be pulled High using an external 4.7-kΩ pull-up to VCCO. Selects serial mode configuration.
CEO D2 Do Not Connect. Leave unconnected.
DNC10 D3 Do Not Connect. Leave unconnected.
DNC11 D4 Do Not Connect. Leave unconnected.
D3 D5 Do Not Connect. Leave unconnected.
VCCO4 D6 P Positive 2.5-V supply voltage connected to the output voltage drivers and internal buffers.
VCCINT2 E1 P Positive 1.8-V supply voltage for internal logic.
TMS E2 I JTAG Mode Select Input. TMS has an internal 50-kΩ resistive pull-up to VCCJ.
DNC4 E3 Do Not Connect. Leave unconnected.
DNC5 E4 Do Not Connect. Leave unconnected.
D2 E5 Do Not Connect. Leave unconnected.
TDO E6 O JTAG Serial Data Output. TDO has an internal 50-kΩ resistive pull-up to VCCJ.
GND F1 G Ground
DNC6 F2 Do Not Connect. Leave unconnected.
DNC7 F3 Do Not Connect. Leave unconnected.
DNC8 F4 Do Not Connect. Leave unconnected.
GND F5 G Ground
GND F6 G Ground
TDI G1 I JTAG Serial Data Input. TDI has an internal 50k-Ω resistive pull-up to VCCJ.
DNC9 G2 Do Not Connect. Leave unconnected.
REV_SEL0 G3 I Revision Select [1:0] Inputs. When the EN_EXT_SEL is Low, the Revision Select pins are used to select the design revision to be enabled. The Revision Select [1:0] inputs have an internal 50-kΩ resistive pull-up to VCCO. The REV_SEL0 pin must be pulled Low using an external 10-kΩ pull-down to Ground. The REV_SEL1 pin must be connected to Ground.
REV_SEL1 G4 I
VCCO3 G5 P Positive 2.5-V supply voltage connected to the output voltage drivers and internal buffers.
VCCINT3 G6 P Positive 1.8-V supply voltage for internal logic.
GND H1 G Ground
VCCJ H2 P Positive 2.5-V JTAG I/O supply voltage connected to the TDO output voltage driver and TCK, TMS and TDI input buffers.
TCK H3 I JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics.
EN_EXT_SEL H4 I External Selection Input. EN_EXT_SEL has an internal 50-kΩ resistive pull- up to VCCO. The EN_EXT_SEL pin must be connected to Ground.
D1 H5 Do Not Connect. Leave unconnected.
D0 H6 O DATA output pin to provide data for configuring the DLPC410 in serial mode.
P = Power, G = Ground, I = Input, O = Output