ZHCSAV5F April   2013  – May 2019 DLPC350

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2. Table 1. Power and Ground Pin Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  I/O Electrical Characteristics
    6. 6.6  I2C0 and I2C1 Interface Timing Requirements
    7. 6.7  Port 1 Input Pixel Interface Timing Requirements
    8. 6.8  Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements
    9. 6.9  System Oscillator Timing Requirements
    10. 6.10 Reset Timing Requirements
    11. 6.11 Video Timing Input Blanking Specification
      1. 6.11.1 Source Input Blanking
    12. 6.12 Programmable Output Clocks Switching Characteristics
    13. 6.13 DMD Interface Switching Characteristics
    14. 6.14 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Power Consumption
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Board Level Test Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 Structured Light Applications
      2. 8.4.2 (LVDS) Receiver Supported Pixel Mapping Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Chipset Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 DLPC350 System Interfaces
            1. 9.2.1.2.1.1 Control Interface
            2. 9.2.1.2.1.2 Input Data Interface
          2. 9.2.1.2.2 DLPC350 System Output Interfaces
            1. 9.2.1.2.2.1 Illumination Interface
            2. 9.2.1.2.2.2 Trigger Interface (Sync Outputs)
          3. 9.2.1.2.3 DLPC350 System Support Interfaces
            1. 9.2.1.2.3.1 Reference Clock
            2. 9.2.1.2.3.2 PLL
            3. 9.2.1.2.3.3 Program Memory Flash Interface
          4. 9.2.1.2.4 DMD Interfaces
            1. 9.2.1.2.4.1 DLPC350 to DMD Digital Data
            2. 9.2.1.2.4.2 DLPC350 to DMD Control Interface
            3. 9.2.1.2.4.3 DLPC350 to DMD Micromirror Reset Control Interface
  10. 10Power Supply Recommendations
    1. 10.1 System Power and Reset
      1. 10.1.1 Default Conditions
        1. 10.1.1.1 1.2-V System Power
        2. 10.1.1.2 1.8-V System Power
        3. 10.1.1.3 1.9-V System Power
        4. 10.1.1.4 3.3-V System Power
        5. 10.1.1.5 FPD-Link Input LVDS System Power
      2. 10.1.2 System Power-up and Power-down Sequence
      3. 10.1.3 Power-On Sense (POSENSE) Support
      4. 10.1.4 Power-Good (PWRGOOD) Support
      5. 10.1.5 5-V Tolerant Support
      6. 10.1.6 Power Reset Operation
      7. 10.1.7 System Reset Operation
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DMD Interface Design Considerations
      2. 11.1.2 DMD Termination Requirements
      3. 11.1.3 Decoupling Capacitors
      4. 11.1.4 Power Plane Recommendations
      5. 11.1.5 Signal Layer Recommendations
      6. 11.1.6 General Handling Guidelines for CMOS-Type Pins
      7. 11.1.7 PCB Manufacturing
        1. 11.1.7.1 General Guidelines
        2. 11.1.7.2 Trace Widths and Minimum Spacings
        3. 11.1.7.3 Routing Constraints
        4. 11.1.7.4 Fiducials
        5. 11.1.7.5 Flex Considerations
        6. 11.1.7.6 DLPC350 Thermal Considerations
    2. 11.2 Layout Example
      1. 11.2.1 Printed Circuit Board Layer Stackup Geometry
      2. 11.2.2 Recommended DLPC350 MOSC Crystal Oscillator Configuration
      3. 11.2.3 Recommended DLPC350 PLL Layout Configuration
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 视频时序参数定义
      2. 12.1.2 器件命名规则
      3. 12.1.3 器件标记
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 商标
    4. 12.4 Glossary
  13. 13机械、封装和可订购信息
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

7.1 Power Consumption

Table 5 lists the typical current and power consumption of the individual supplies.

Normal mode refers to operation during full functionality, active product operation. Typical values correspond to power dissipated on nominal process devices operating at nominal voltage and 70°C junction temperature (approximately 25°C ambient) displaying typical video-graphics content from a high frequency source. Maximum values correspond to power dissipated on fast process devices operating at high voltage and 105°C junction temperature (approximately 55°C ambient) displaying typical video-graphics content from a high-frequency source. The increased power dissipation observed on fast process devices operated at maximum recommended temperatures is primarily a result of increased leakage current. Maximum power values are estimates and may not reflect the actual final power consumption of the device.

Table 5. Power Consumption

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ICC12 Supply voltage, 1.2-V core power Normal Mode 600 1020 mA
ICC19_DMD Supply voltage, 1.9-V I/O power (DMD LPDDR) Normal Mode 30 50 mA
ICC33 Supply voltage, 3.3-V (I/O) power Normal Mode 40 70 mA
ICC12_FPD FPD-Link LVDS interface supply voltage, 1.2-V power Normal Mode 60 100 mA
ICC33_FPD FPD-Link LVDS interface supply voltage, 3.3-V power Normal Mode 50 85 mA
ICC12_PLLD Supply voltage, PLL digital power (1.2 V) Normal Mode 9 15 mA
ICC12_PLLM Supply voltage, master clock generator PLL digital power (1.2 V) Normal Mode 9 15 mA
ICC18_PLLD Supply voltage, PLL analog power (1.8 V) Normal Mode 10 15 mA
ICC18_PLLM Supply voltage, master clock generator PLL analog power (1.8 V) Normal Mode 10 15 mA
Total Power Normal Mode 1225 2200 mW