ZHCSIG4A July 2018 – June 2019 DLPC3434
It is assumed that an external power monitor will hold the DLPC3434 in system reset during power-up. It must do this by driving RESETZ to a logic low state. It should continue to assert system reset until all ASIC voltages have reached minimum specified voltage levels, PARKZ is asserted high, and input clocks are stable. During this time, most ASIC outputs will be driven to an inactive state and all bidirectional signals will be configured as inputs to avoid contention. ASIC outputs that are not driven to an inactive state are tri-stated. These include LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICSZ0 (see RESETZ pin description for full signal descriptions in . After power is stable and the PLL_REFCLK_I clock input to the DLPC3434 is stable, then RESETZ should be deactivated (set to a logic high). The DLPC3434 then performs a power-up initialization routine that first locks its PLL followed by loading self configuration data from the external flash. Upon release of RESETZ all DLPC3434 I/Os will become active. Immediately following the release of RESETZ, the HOST_IRQ signal will be driven high to indicate that the auto initialization routine is in progress. However, since a pullup resistor is connected to signal HOST_IRQ, this signal will have already gone high before the DLPC3434 actively drives it high. Upon completion of the chipset auto-initialization routine, the master DLPC3434 will drive HOST_IRQ low to indicate the initialization done state of the DLPC3434 has been reached.
Note that the host processor must wait for HOST_IRQ to go low before initiating I2C commands.