ZHCSIG4A July   2018  – June 2019 DLPC3434


  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化应用
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions – Board Level Test, Debug, and Initialization
    2.     Pin Functions – Parallel Port Input Data and Control
    3.     Pin Functions – DMD Reset and Bias Control
    4.     Pin Functions – DMD Sub-LVDS Interface
    5.     Pin Functions – Peripheral Interface
    6.     Pin Functions – GPIO Peripheral Interface
    7.     Pin Functions – Clock and PLL Support
    8.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  High-Speed Sub-LVDS Electrical Characteristics
    9. 6.9  Low-Speed SDR Electrical Characteristics
    10. 6.10 System Oscillators Timing Requirements
    11. 6.11 Power-Up and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
  7. Parameter Measurement Information
    1. 7.1 HOST_IRQ Usage Model
    2. 7.2 Input Frame Rates and 3-D Display Operation
      1. 7.2.1 Parallel Interface Data Transfer Format
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Interface Timing Requirements
        1. Parallel Interface
      2. 8.3.2  Serial Flash Interface
      3. 8.3.3  Tested Flash Devices
      4. 8.3.4  Serial Flash Programming
      5. 8.3.5  SPI Signal Routing
      6. 8.3.6  I2C Interface Performance
      7. 8.3.7  Content-Adaptive Illumination Control
      8. 8.3.8  Local Area Brightness Boost
      9. 8.3.9  3-D Glasses Operation
      10. 8.3.10 DMD (Sub-LVDS) Interface
      11. 8.3.11 Calibration and Debug Support
      12. 8.3.12 DMD Interface Considerations
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC3434 Power-Up Initialization Sequence
    3. 10.3 DMD Fast PARK Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2  DLPC3434 Reference Clock
        1. Recommended Crystal Oscillator Configuration
      3. 11.1.3  General PCB Recommendations
      4. 11.1.4  General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6  Number of Layer Changes
      7. 11.1.7  Stubs
      8. 11.1.8  Terminations
      9. 11.1.9  Routing Vias
      10. 11.1.10 Thermal Considerations
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
      2. 12.1.2 器件命名规则
        1. 器件标记
      3. 12.1.3 视频时序参数定义
    2. 12.2 相关链接
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information


机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)

Content-Adaptive Illumination Control

Content-adaptive illumination control (CAIC) is an image processing algorithm that takes advantage of the fact that in common real-world image content most pixels in the images are well below full scale for the for the R, G, and B digital channels being input to the DLPC3434. As a result of this the average picture level (APL) for the overall image is also well below full scale, and the system’s dynamic range for the collective set of pixel values is not fully utilized. CAIC takes advantage of this headroom between the source image APL and the top of the available dynamic range of the display system.

CAIC evaluates images frame by frame and derives three unique digital gains, one for each of the R, G, and B color channels. During CAIC image processing, each gain is applied to all pixels in the associated color channel. CAIC derives each color channel’s gain that is applied to all pixels in that channel so that the pixels as a group collectively shift upward and as close to full scale as possible. To prevent any image quality degradation, the gains are set at the point where just a few pixels in each color channel are clipped. Figure 11 and Figure 12 show an example of the application of CAIC for one color channel.

DLPC3434 input_pixel_ex_LPS038.gifFigure 11. Input Pixels Example
DLPC3434 display_pix_CAIC_LPS038.gifFigure 12. Displayed Pixels After CAIC Processing

Figure 12 shows the gain that is applied to a color processing channel inside the DLPC3434. CAIC will also adjust the power for the R, G, and B LED. For each color channel of an individual frame, CAIC will intelligently determine the optimal combination of digital gain and LED power. The decision regarding how much digital gain to apply to a color channel and how much to adjust the LED power for that color is heavily influenced by the software command settings sent to the DLPC3434 for configuring CAIC.

As CAIC applies a digital gain to each color channel independently, and adjusts each LED’s power independently, CAIC also makes sure that the resulting color balance in the final image matches the target color balance for the projector system. Thus, the effective displayed white point of images is held constant by CAIC from frame to frame.

Since the R, G, and B channels can be gained up by CAIC inside the DLPC3434, the LED power can be turned down for any color channel until the brightness of the color on the screen is unchanged. Thus, CAIC can achieve an overall LED power reduction while maintaining the same overall image brightness as if CAIC was not used. Figure 13 shows an example of LED power reduction by CAIC for an image where the R and B LEDs can be turned down in power.

CAIC can alternatively be used to increase the overall brightness of an image while holding the total power for all LEDs constant. In summary, when CAIC is enabled CAIC can operate in one of two distinct modes:

  • Power Reduction Mode – holds overall image brightness constant while reducing LED power
  • Enhanced Brightness Mode – holds overall LED power constant while enhancing image brightness
DLPC3434 CAIC_pwr_reduc_LPS038.gifFigure 13. CAIC Power Reduction Mode (for Constant Brightness)