ZHCSIG4A July 2018 – June 2019 DLPC3434
The parallel interface complies with standard graphics interface protocol, with the addition of the SUB_FRAME signal (which is a necessary output from the LFE5U-85F-7BG381CAMK FPGA). The standard graphics interface protocol includes a vertical sync signal (VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid signal (DATAEN_CMD), a 24-bit data bus (PDATA), and a pixel clock (PCLK). The polarity of both syncs and the active edge of the clock are programmable. Figure 4 shows the relationship of these signals.
VSYNC_WE must remain active at all times (in lock-to-VSYNC mode) or the display sequencer will stop and cause the LEDs to be turned off.