ZHCSIG4A July   2018  – June 2019 DLPC3434

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化应用
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions – Board Level Test, Debug, and Initialization
    2.     Pin Functions – Parallel Port Input Data and Control
    3.     Pin Functions – DMD Reset and Bias Control
    4.     Pin Functions – DMD Sub-LVDS Interface
    5.     Pin Functions – Peripheral Interface
    6.     Pin Functions – GPIO Peripheral Interface
    7.     Pin Functions – Clock and PLL Support
    8.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  High-Speed Sub-LVDS Electrical Characteristics
    9. 6.9  Low-Speed SDR Electrical Characteristics
    10. 6.10 System Oscillators Timing Requirements
    11. 6.11 Power-Up and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
  7. Parameter Measurement Information
    1. 7.1 HOST_IRQ Usage Model
    2. 7.2 Input Frame Rates and 3-D Display Operation
      1. 7.2.1 Parallel Interface Data Transfer Format
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Interface Timing Requirements
        1. 8.3.1.1 Parallel Interface
      2. 8.3.2  Serial Flash Interface
      3. 8.3.3  Tested Flash Devices
      4. 8.3.4  Serial Flash Programming
      5. 8.3.5  SPI Signal Routing
      6. 8.3.6  I2C Interface Performance
      7. 8.3.7  Content-Adaptive Illumination Control
      8. 8.3.8  Local Area Brightness Boost
      9. 8.3.9  3-D Glasses Operation
      10. 8.3.10 DMD (Sub-LVDS) Interface
      11. 8.3.11 Calibration and Debug Support
      12. 8.3.12 DMD Interface Considerations
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC3434 Power-Up Initialization Sequence
    3. 10.3 DMD Fast PARK Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2  DLPC3434 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3  General PCB Recommendations
      4. 11.1.4  General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6  Number of Layer Changes
      7. 11.1.7  Stubs
      8. 11.1.8  Terminations
      9. 11.1.9  Routing Vias
      10. 11.1.10 Thermal Considerations
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
      2. 12.1.2 器件命名规则
        1. 12.1.2.1 器件标记
      3. 12.1.3 视频时序参数定义
    2. 12.2 相关链接
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Parallel Interface Frame Timing Requirements

MIN MAX UNIT
tp_vsw Pulse duration – VSYNC_WE high 50% reference points 1 lines
tp_vbp Vertical back porch (VBP) – time from the leading edge of VSYNC_WE to the leading edge HSYNC_CS for the first active line (see (1)) 50% reference points 2 lines
tp_vfp Vertical front porch (VFP) – time from the leading edge of the HSYNC_CS following the last active line in a frame to the leading edge of VSYNC_WE (see (1)) 50% reference points 1 lines
tp_tvb Total vertical blanking – time from the leading edge of HSYNC_CS following the last active line of one frame to the leading edge of HSYNC_CS for the first active line in the next frame. (This is equal to the sum of VBP (tp_vbp) + VFP (tp_vfp).) 50% reference points See (1) lines
tp_hsw Pulse duration – HSYNC_CS high 50% reference points 4 128 PCLKs
tp_hbp Horizontal back porch – time from rising edge of HSYNC_CS to rising edge of DATAEN_CMD 50% reference points 4 PCLKs
tp_hfp Horizontal front porch – time from falling edge of DATAEN_CMD to rising edge of HSYNC_CS 50% reference points 8 PCLKs
tp_thb Total horizontal blanking – sum of horizontal front and back porches 50% reference points See (2) PCLKs
The minimum total vertical blanking is defined by the following equation: tp_tvb(min) = 6 + [6 × Max(1, Source_ALPF/ DMD_ALPF)] lines
where:
  • SOURCE_ALPF = Input source active lines per frame
  • DMD_ALPF = Actual DMD used lines per frame supported
Total horizontal blanking is driven by the maximum line rate for a given source which will be a function of resolution and orientation. The following equation can be applied for this: tp_thb = Roundup[(1000 × ƒclock)/ LR] – APPL
where:
  • ƒclock = Pixel clock rate in MHz
  • LR = Line rate in kHz
  • APPL is the number of active pixels per (horizontal) line.
  • If tp_thb is calculated to be less than tp_hbp + tp_hfp then the pixel clock rate is too low or the line rate is too high, and one or both must be adjusted.
DLPC3434 tim_par_frame_LPS038.gifFigure 4. Parallel Interface Frame Timing