ZHCSIG4A July   2018  – June 2019 DLPC3434

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化应用
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions – Board Level Test, Debug, and Initialization
    2.     Pin Functions – Parallel Port Input Data and Control
    3.     Pin Functions – DMD Reset and Bias Control
    4.     Pin Functions – DMD Sub-LVDS Interface
    5.     Pin Functions – Peripheral Interface
    6.     Pin Functions – GPIO Peripheral Interface
    7.     Pin Functions – Clock and PLL Support
    8.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  High-Speed Sub-LVDS Electrical Characteristics
    9. 6.9  Low-Speed SDR Electrical Characteristics
    10. 6.10 System Oscillators Timing Requirements
    11. 6.11 Power-Up and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
  7. Parameter Measurement Information
    1. 7.1 HOST_IRQ Usage Model
    2. 7.2 Input Frame Rates and 3-D Display Operation
      1. 7.2.1 Parallel Interface Data Transfer Format
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Interface Timing Requirements
        1. 8.3.1.1 Parallel Interface
      2. 8.3.2  Serial Flash Interface
      3. 8.3.3  Tested Flash Devices
      4. 8.3.4  Serial Flash Programming
      5. 8.3.5  SPI Signal Routing
      6. 8.3.6  I2C Interface Performance
      7. 8.3.7  Content-Adaptive Illumination Control
      8. 8.3.8  Local Area Brightness Boost
      9. 8.3.9  3-D Glasses Operation
      10. 8.3.10 DMD (Sub-LVDS) Interface
      11. 8.3.11 Calibration and Debug Support
      12. 8.3.12 DMD Interface Considerations
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC3434 Power-Up Initialization Sequence
    3. 10.3 DMD Fast PARK Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2  DLPC3434 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3  General PCB Recommendations
      4. 11.1.4  General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6  Number of Layer Changes
      7. 11.1.7  Stubs
      8. 11.1.8  Terminations
      9. 11.1.9  Routing Vias
      10. 11.1.10 Thermal Considerations
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
      2. 12.1.2 器件命名规则
        1. 12.1.2.1 器件标记
      3. 12.1.3 视频时序参数定义
    2. 12.2 相关链接
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Electrical Characteristics over Recommended Operating Conditions

see (1)(2)(3)
PARAMETER TEST CONDITIONS(4)(5) MIN TYP(6) MAX(7) UNIT
I(VDD) Core current 1.1 V (main 1.1 V) IDLE disabled, 1280 x 720, 60 Hz 232.2 mA
I(VDD_PLLM) MCG PLL 1.1-V current IDLE disabled, 1280 x 720, 60 Hz 6 mA
I(VDD_PLLD) DCG PLL 1.1-V current IDLE disabled, 1280 x 720, 60 Hz 6 mA
I(VDD) + I(VDD_PLLM) + I(VDD_PLLD) Core Current 1.1 V + MCG PLL 1.1-V current + DCG PLL 1.1-V current IDLE disabled, 1280 x 720, 60 Hz 112 244.2 mA
I(VCC18) Main 1.8-V I/O current: 1.8-V power supply for all I/O other than the host or parallel interface and the SPI flash interface.
This includes sub-LVDS DMD I/O , RESETZ, PARKZ, LED_SEL, CMP, GPIO, IIC1, TSTPT and JTAG pins
IDLE disabled, 1280 x 720, 60 Hz 9.6 mA
I(VCC_INTF) Host or parallel interface I/O current: 1.8 V ( includes IIC0, PDATA, video syncs, and HOST_IRQ pins) IDLE disabled, 1280 x 720, 60 Hz 1.5 mA
I(VCC_FLSH) Flash Interface I/O current: 1.8 V to 3.3 V IDLE disabled, 1280 x 720, 60 Hz 1.01 mA
I(VCC18) +
I(VCC_INTF) +
I(VCC_FLSH)
Main 1.8 V I/O current + VCC_INTF current + VCC_FLSH current IDLE disabled, 1280 x 720, 60 Hz 13 15.13 mA
Programmable host and flash I/O are at minimum voltage (that is 1.8 V) for this typical scenario.
Max currents column use typical motion video as the input. The typical currents column uses SMPTE color bars as the input.
Some applications may be forced to use 1-oz. copper to manage ASIC package heat.
Chipset input image is 1280 x 720 (720p) 24-bits on the FPGA parallel interface at the frame rate shown with a 0.23-inch 720p DMD.
In normal operation while displaying an image with CAIC enabled. "IDLE" is a low-power mode that is disabled in normal operation.
Assumes typical case power PVT condition = nominal process, typical voltage, typical temperature (55°C junction), a 0.23-inch 720p DMD.
Assumes worse case power PVT condition = corner process, high voltage, high temperature (105°C junction), a 0.23-inch 720p DMD.