ZHCSJ26 November   2018 DLP3310

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化应用
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions – Connector Pins
    2.     Pin Functions – Test Pads
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
    14. 6.14 Software Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
      2. 11.1.2 器件标记
    2. 11.2 相关链接
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
  • FQM|92
订购信息

Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT
CURRENT
IDD Supply current: VDD(3)(4) VDD = 1.95 V 135 mA
VDD = 1.8 V 123.6
IDDI Supply current: VDDI(3)(4) VDDI = 1.95 V 35.34 mA
VDD = 1.8 V 32
IOFFSET Supply current: VOFFSET(5)(6) VOFFSET = 10.5 V 2.55 mA
VOFFSET = 10 V 2.5
IBIAS Supply current: VBIAS(5)(6) VBIAS = 18.5 V 1.25 mA
VBIAS = 18 V 1.2
IRESET Supply current: VRESET(6) VRESET = –14.5 V –2.55 mA
VRESET = –14 V –2.5
POWER(7)
PDD Supply power dissipation: VDD(3)(4) VDD = 1.95 V 263.25 mW
VDD = 1.8 V 222.48
PDDI Supply power dissipation: VDDI(3)(4) VDDI = 1.95 V 68.91 mW
VDD = 1.8 V 57.6
POFFSET Supply power dissipation: VOFFSET(5)(6) VOFFSET = 10.5 V 26.78 mW
VOFFSET = 10 V 25
PBIAS Supply power dissipation: VBIAS(5)(6) VBIAS = 18.5 V 23.13 mW
VBIAS = 18 V 21.6
PRESET Supply power dissipation: VRESET(6) VRESET = –14.5 V 36.98 mW
VRESET = –14 V 35
PTOTAL Supply power dissipation: Total 361.68 419.05 mW
LPSDR INPUT(8)
VIH(DC) DC input high voltage(9) 0.7 × VDD VDD + 0.3 V
VIL(DC) DC input low voltage(9) –0.3 0.3 × VDD V
VIH(AC) AC input high voltage(9) 0.8 × VDD VDD + 0.3 V
VIL(AC) AC input low voltage(9) –0.3 0.2 × VDD V
∆VT Hysteresis ( VT+ – VT– ) Figure 10 0.1 × VDD 0.4 × VDD V
IIL Low–level input current VDD = 1.95 V; VI = 0 V –100 nA
IIH High–level input current VDD = 1.95 V; VI = 1.95 V 100 nA
LPSDR OUTPUT(10)
VOH DC output high voltage IOH = –2 mA 0.8 × VDD V
VOL DC output low voltage IOL = 2 mA 0.2 × VDD V
CAPACITANCE
CIN Input capacitance LPSDR ƒ = 1 MHz 10 pF
Input capacitance SubLVDS ƒ = 1 MHz 20 pF
COUT Output capacitance ƒ = 1 MHz 10 pF
CRESET Reset group capacitance ƒ = 1 MHz; (768 × 344) micromirrors 400 500 pF
Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
All voltage values are with respect to the ground pins (VSS).
To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
Supply power dissipation based on non–compressed commands and data.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
Supply power dissipation based on 3 global resets in 200 µs.
The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.
LPSDR specifications are for pins LS_CLK and LS_WDATA.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
LPSDR specification is for pin LS_RDATA.