6.4 Recommended Operating ConditionsOver operating free-air temperature range (unless otherwise noted)(1)(2)
| ||MIN ||NOM ||MAX ||UNIT |
|SUPPLY VOLTAGE RANGE(3) |
|VDD ||Supply voltage for LVCMOS core logic |
Supply voltage for LPSDR low-speed interface
|1.65 ||1.8 ||1.95 ||V |
|VDDI ||Supply voltage for SubLVDS receivers ||1.65 ||1.8 ||1.95 ||V |
|VOFFSET ||Supply voltage for HVCMOS and micromirror electrode(4) ||9.5 ||10 ||10.5 ||V |
|VBIAS ||Supply voltage for mirror electrode ||17.5 ||18 ||18.5 ||V |
|VRESET ||Supply voltage for micromirror electrode ||–14.5 ||–14 ||–13.5 ||V |
||VDDI–VDD| ||Supply voltage delta (absolute value)(5) || || ||0.3 ||V |
||VBIAS–VOFFSET| ||Supply voltage delta (absolute value)(6) || || ||10.5 ||V |
||VBIAS–VRESET| ||Supply voltage delta (absolute value)(7) || || ||33 ||V |
|CLOCK FREQUENCY |
|ƒclock ||Clock frequency for low speed interface LS_CLK(8) ||108 || ||120 ||MHz |
|ƒclock ||Clock frequency for high speed interface DCLK(9) ||300 || ||540 ||MHz |
| ||Duty cycle distortion DCLK ||44% || ||56% || |
|SUBLVDS INTERFACE(9) |
||VID| ||SubLVDS input differential voltage (absolute value). See Figure 8. Figure 9 ||150 ||250 ||350 ||mV |
|VCM ||Common mode voltage. See Figure 8. Figure 9 ||700 ||900 ||1100 ||mV |
|VSUBLVDS ||SubLVDS voltage. See Figure 8. Figure 9 ||575 || ||1225 ||mV |
|ZLINE ||Line differential impedance (PWB/trace) ||90 ||100 ||110 ||Ω |
|ZIN ||Internal differential termination resistance. See Figure 10 ||80 ||100 ||120 ||Ω |
| ||100-Ω differential PCB trace ||6.35 || ||152.4 ||mm |
|TARRAY ||Array temperature – long-term operational(10)(11)(12)(13) ||0 || ||40 to 70(12) ||°C |
|Array temperature – short-term operational, 25 hr max(11)(14) ||–20 || ||–10 ||°C |
|Array temperature – short-term operational, 500 hr max(11)(14) ||–10 || ||0 ||°C |
|Array temperature – short-term operational, 500 hr max(11)(14) ||70 || ||75 ||°C |
|TWINDOW ||Window temperature – operational (15)(16) || || ||90 ||°C |
||TDELTA| ||Absolute temperature delta between any point on the window edge and the ceramic test point TP1(17) || || ||30 ||°C |
|TDP-AVG ||Average dew point temperature, non-condensing(18) || || ||24 ||°C |
|TDP-ELR ||Elevated dew point temperature range, non-condensing(19) ||28 || ||36 ||°C |
|CTELR ||Cumulative time in elevated dew point temperature range. || || ||6 ||Months |
|ILLUV ||Illumination wavelengths < 420 nm (10) || || ||0.68 ||mW/cm2 |
|ILLVIS ||Illumination wavelengths between 420 nm and 700 nm ||Thermally Limited || |
|ILLIR ||Illumination wavelengths > 700 nm || || ||10 ||mW/cm2 |
|ILLθ ||Illumination marginal ray angle (16) || || ||55 ||degrees |
(1) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(3) All voltage values are with respect to the ground pins (VSS).
(4) VOFFSET supply transients must fall within specified max voltages.
(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than the specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit.
(7) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit.
(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
(10) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will reduce device lifetime.
Per Figure 1
, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle
for a definition of micromirror landed duty cycle.
(13) Long-term is defined as the useful life of the device.
(14) Short-term is the total cumulative time over the useful life of the device.
The locations of thermal test points TP2, TP3, TP4, and TP5 shown in Figure 18
are intended to measure the highest window edge temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(16) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 18
. The window test points TP2, TP3, TP4, and TP5 shown in Figure 18
are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
(18) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(19) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR.
Figure 1. Maximum Recommended Array Temperature – Derating Curve