ZHCSIP9A July   2018  – September 2018 DLP230KP

PRODUCTION DATA.  

  1. 特性
  2. 显示 应用
  3. 说明
    1.     Device Images
      1.      简化应用
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions – Connector Pins
    2.     Pin Functions – Test Pads
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Micromirror Array Physical Characteristics
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Interface
      2. 7.3.2 Low-Speed Interface
      3. 7.3.3 High-Speed Interface
      4. 7.3.4 Timing
    4. 7.4 Device Functional Modes
    5. 7.5 Optical Interface and System Image Quality Considerations
      1. 7.5.1 Numerical Aperture and Stray Light Control
      2. 7.5.2 Pupil Match
      3. 7.5.3 Illumination Overfill
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 7.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 7.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
      2. 11.1.2 器件标记
    2. 11.2 相关链接
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Timing Requirements

Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted.
MIN NOM MAX UNIT
LPSDR
tr Rise slew rate(1) (30% to 80%) × VDD, Figure 3 1 3 V/ns
tƒ Fall slew rate(1) (70% to 20%) × VDD, Figure 3 1 3 V/ns
tr Rise slew rate(2) (20% to 80%) × VDD, Figure 3 0.25 V/ns
tƒ Fall slew rate(2) (80% to 20%) × VDD, Figure 3 0.25 V/ns
tc Cycle time LS_CLK Figure 2 7.7 8.3 ns
tW(H) Pulse duration LS_CLK high 50% to 50% reference points, Figure 2 3.1 ns
tW(L) Pulse duration LS_CLK low 50% to 50% reference points, Figure 2 3.1 ns
tsu Setup time LS_WDATA valid before LS_CLK ↑, Figure 2 1.5 ns
th Hold time LS_WDATA valid after LS_CLK ↑, Figure 2 1.5 ns
tWINDOW Window time(1)(3) Setup time + hold time, Figure 2 3 ns
tDERATING Window time derating(1)(3) For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 5 0.35 ns
SubLVDS
tr Rise slew rate 20% to 80% reference points, Figure 4 0.7 1 V/ns
tƒ Fall slew rate 80% to 20% reference points, Figure 4 0.7 1 V/ns
tc Cycle time DCLK Figure 6 1.79 1.85 ns
tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 6 0.79 ns
tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 6 0.79 ns
tsu Setup time D(0:7) valid before
DCLK ↑ or DCLK ↓, Figure 6
th Hold time D(0:7) valid after
DCLK ↑ or DCLK ↓, Figure 6
tWINDOW Window time Setup time + hold time, Figure 6, Figure 7 0.3 ns
tLVDS-ENABLE+REFGEN Power-up receiver(4) 2000 ns
Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 3.
Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 3.
Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.
Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
DLP230KP FG08.gif
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR)JESD209B.
Figure 2. LPSDR Switching Parameters
DLP230KP FG09.gifFigure 3. LPSDR Input Rise and Fall Slew Rate
DLP230KP visio_p23_qhd_s246_sublvds_rise_time_fall_time_slew_rate.gifFigure 4. SubLVDS Input Rise and Fall Slew Rate
DLP230KP tim_wind_derating_LPS046.gifFigure 5. Window Time Derating Concept
DLP230KP visio_p23_qhd_s246_sublvds_switching_parameters.gifFigure 6. SubLVDS Switching Parameters
DLP230KP visio_p23_qhd_s246_sublvds_high_speed_training_window.gif
Note: Refer to High-Speed Interface for details.
Figure 7. High-Speed Training Scan Window
DLP230KP visio_p23_qhd_s246_sublvds_voltage_parameters.gifFigure 8. SubLVDS Voltage Parameters
DLP230KP FG02.gifFigure 9. SubLVDS Waveform Parameters
DLP230KP visio_p23_qhd_s246_sublvds_equivalent_input_circuit.gifFigure 10. SubLVDS Equivalent Input Circuit
DLP230KP FG05.gifFigure 11. LPSDR Input Hysteresis
DLP230KP FG06.gifFigure 12. LPSDR Read Out
DLP230KP FG07.gif
See Timing for more information.
Figure 13. Test Load Circuit for Output Propagation Measurement