ZHCSHR4F January   2009  – April 2018 DAC7568 , DAC8168 , DAC8568

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Electrical Characteristics
    3. 7.3 Timing Requirements
    4. 7.4 Typical Characteristics: Internal Reference
    5. 7.5 Typical Characteristics: DAC at AVDD = 5.5 V
    6. 7.6 Typical Characteristics: DAC at AVDD = 3.6 V
    7. 7.7 Typical Characteristics: DAC at AVDD = 2.7 V
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Digital-to-Analog Converter (DAC)
      2. 8.2.2  Resistor String
      3. 8.2.3  Output Amplifier
      4. 8.2.4  Internal Reference
      5. 8.2.5  Serial Interface
      6. 8.2.6  Input Shift Register
        1. Table 1. DAC8568 Data Input Register Format
        2. Table 2. DAC8168 Data Input Register Format
        3. Table 3. DAC7568 Data Input Register Format
      7. 8.2.7  SYNC Interrupt
      8. 8.2.8  Power-on Reset to Zero Scale or Midscale
      9. 8.2.9  Clear Code Register and CLR Pin
      10. 8.2.10 Software Reset Function
      11. 8.2.11 Operating Examples: DAC7568/DAC8168/DAC8568
        1. Table 4.   1st: Write to Data Buffer A:
        2. Table 5.   2nd: Write to Data Buffer B:
        3. Table 6.   3rd: Write to Data Buffer G:
        4. Table 7.   4th: Write to Data Buffer H and Simultaneously Update all DACs:
        5. Table 8.   1st: Write to Data Buffer C and Load DAC C: DAC C Output Settles to Specified Value Upon Completion:
        6. Table 9.   2nd: Write to Data Buffer D and Load DAC D: DAC D Output Settles to Specified Value Upon Completion:
        7. Table 10. 3rd: Write to Data Buffer E and Load DAC E: DAC E Output Settles to Specified Value Upon Completion:
        8. Table 11. 4th: Write to Data Buffer F and Load DAC F: DAC F Output Settles to Specified Value Upon Completion:
        9. Table 12. 1st: Write Power-Down Command to DAC Channel A and DAC Channel B: DAC A and DAC B to 1kΩ.
        10. Table 13. 2nd: Write Power-Down Command to DAC Channel H: DAC H to 1kΩ.
        11. Table 14. 3rd: Write Power-Down Command to DAC Channel C and DAC Channel D: DAC C and DAC D to 100kΩ.
        12. Table 15. 4th: Write Power-Down Command to DAC Channel F: DAC F to 100kΩ.
        13. Table 16. 1st: Write Sequence for Enabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time:
        14. Table 17. 2nd: Write Sequence to Power-Down All DACs to High-Impedance:
        15. Table 18. 1st: Write Sequence for Disabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time (after this sequence, these devices require an external reference source to function):
        16. Table 19. 2nd: Write Sequence to Write Specified Data to All DACs:
    3. 8.3 Device Functional Modes
      1. 8.3.1 Enable/Disable Internal Reference
        1. 8.3.1.1 Static Mode
          1. Table 20. Write Sequence for Enabling Internal Reference (Static Mode) (Internal Reference Powered On—08000001h)
          2. Table 21. Write Sequence for Disabling Internal Reference (Static Mode) (Internal Reference Powered On—08000000h)
        2. 8.3.1.2 Flexible Mode
          1. Table 22. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Powered On—09080000h)
          2. Table 23. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Always Powered On—090A0000h)
          3. Table 24. Write Sequence for Disabling Internal Reference (Flexible Mode) (Internal Reference Always Powered Down—090C0000h)
          4. Table 25. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference (Internal Reference Always Powered Down—09000000h)
      2. 8.3.2 LDAC Functionality
      3. 8.3.3 Power-Down Modes
        1. 8.3.3.1 DAC Power-Down Commands
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications - Microprocessor Interfacing
      1. 9.2.1 DAC7568/DAC8168/DAC8568 to an 8051 Interface
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Internal Reference
            1. 9.2.1.1.1.1 Supply Voltage
            2. 9.2.1.1.1.2 Temperature Drift
            3. 9.2.1.1.1.3 Noise Performance
            4. 9.2.1.1.1.4 Load Regulation
            5. 9.2.1.1.1.5 Long-Term Stability
            6. 9.2.1.1.1.6 Thermal Hysteresis
          2. 9.2.1.1.2 DAC Noise Performance
          3. 9.2.1.1.3 Bipolar Operation Using The DAC7568/DAC8168/DAC8568
      2. 9.2.2 DAC7568/DAC8168/DAC8568 to Microwire Interface
      3. 9.2.3 DAC7568/DAC8168/DAC8568 to 68HC11 Interface
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
        1. 11.1.1.1 静态性能
          1. 11.1.1.1.1  分辨率
          2. 11.1.1.1.2  最低有效位 (LSB)
          3. 11.1.1.1.3  最高有效位 (MSB)
          4. 11.1.1.1.4  相对精度或积分非线性 (INL)
          5. 11.1.1.1.5  微分非线性 (DNL)
          6. 11.1.1.1.6  满量程误差
          7. 11.1.1.1.7  偏移误差
          8. 11.1.1.1.8  零代码误差
          9. 11.1.1.1.9  增益误差
          10. 11.1.1.1.10 满量程误差漂移
          11. 11.1.1.1.11 偏移误差漂移
          12. 11.1.1.1.12 零代码误差漂移
          13. 11.1.1.1.13 增益温度系数
          14. 11.1.1.1.14 电源抑制比 (PSRR)
          15. 11.1.1.1.15 单调性
        2. 11.1.1.2 动态性能
          1. 11.1.1.2.1  压摆率
          2. 11.1.1.2.2  输出电压稳定时间
          3. 11.1.1.2.3  代码更改/数模转换毛刺脉冲能量
          4. 11.1.1.2.4  数字馈通
          5. 11.1.1.2.5  通道到通道直流串扰
          6. 11.1.1.2.6  通道到通道交流串扰
          7. 11.1.1.2.7  信噪比 (SNR)
          8. 11.1.1.2.8  总谐波失真 (THD)
          9. 11.1.1.2.9  无杂散动态范围 (SFDR)
          10. 11.1.1.2.10 信噪比和失真率 (SINAD)
          11. 11.1.1.2.11 DAC 输出噪声密度
          12. 11.1.1.2.12 DAC 输出噪声
          13. 11.1.1.2.13 满量程范围 (FSR)
    2. 11.2 相关链接
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.2.11 Operating Examples: DAC7568/DAC8168/DAC8568

For the following examples X = don't care; value can be either '0' or '1'.

Example 1: Write to Data Buffer A, B, G, H; Load DAC A, B, G, H Simultaneously

Table 4. 1st: Write to Data Buffer A:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 0 0 0 0 0 0 0 DATA X X X X

Table 5. 2nd: Write to Data Buffer B:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 0 0 0 0 0 0 1 DATA X X X X

Table 6. 3rd: Write to Data Buffer G:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 0 0 0 0 1 1 0 DATA X X X X

Table 7. 4th: Write to Data Buffer H and Simultaneously Update all DACs:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 0 1 0 0 1 1 1 DATA X X X X

The DAC A, DAC B, DAC G, and DAC H analog outputs simultaneously settle to the specified values upon completion of the 4th write sequence. (The DAC voltages update simultaneously after the 32nd SCLK falling edge of the fourth write cycle).

Example 2: Load New Data to DAC C, D, E, F Sequentially

Table 8. 1st: Write to Data Buffer C and Load DAC C: DAC C Output Settles to Specified Value Upon Completion:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 0 1 1 0 0 1 0 DATA X X X X

Table 9. 2nd: Write to Data Buffer D and Load DAC D: DAC D Output Settles to Specified Value Upon Completion:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 0 1 1 0 0 1 1 DATA X X X X

Table 10. 3rd: Write to Data Buffer E and Load DAC E: DAC E Output Settles to Specified Value Upon Completion:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 0 1 1 0 1 0 0 DATA X X X X

Table 11. 4th: Write to Data Buffer F and Load DAC F: DAC F Output Settles to Specified Value Upon Completion:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 0 1 1 0 1 0 1 DATA X X X X

After completion of each write cycle, the DAC analog output settles to the voltage specified.

Example 3: Power-Down DAC A, DAC B and DAC H to 1kΩ and Power-Down DAC C, DAC D, and DAC F to 100kΩ

Table 12. 1st: Write Power-Down Command to DAC Channel A and DAC Channel B: DAC A and DAC B to 1kΩ.

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1

Table 13. 2nd: Write Power-Down Command to DAC Channel H: DAC H to 1kΩ.

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0

Table 14. 3rd: Write Power-Down Command to DAC Channel C and DAC Channel D: DAC C and DAC D to 100kΩ.

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0

Table 15. 4th: Write Power-Down Command to DAC Channel F: DAC F to 100kΩ.

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0

The DAC A, DAC B, DAC C, DAC D, DAC F, and DAC H analog outputs power-down to each respective specified mode.

Example 4: Power-Down All Channels Simultaneously while Reference is Always Powered Up

Table 16. 1st: Write Sequence for Enabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16-DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16 D15 D14 D13-D4 D3 D2 D1 F3 F2 F1 F0
0 X 1 0 0 1 X X X X 1 0 1 X X X X X X X X

Table 17. 2nd: Write Sequence to Power-Down All DACs to High-Impedance:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 1 0 0 X X X X X 1 1 1 1 1 1 1 1 1 1

The DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC G, and DAC H analog outputs simultaneously power-down to high-impedance upon completion of the first and second write sequences, respectively.

Example 5: Write a Specific Value to All DACs while Reference is Always Powered Down

Table 18. 1st: Write Sequence for Disabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time (after this sequence, these devices require an external reference source to function):

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16-DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16 D15 D14 D13-D4 D3 D2 D1 F3 F2 F1 F0
0 X 1 0 0 1 X X X X 1 1 0 X X X X X X X X

Table 19. 2nd: Write Sequence to Write Specified Data to All DACs:

DB31 DB30- DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19- DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 Don't Care C3 C2 C1 C0 A3 A2 A1 A0 D16-D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0
0 X 0 0 1 1 1 1 1 1 DATA X X X X

The DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC G, and DAC H analog outputs simultaneously settle to the specified values upon completion of the second write sequence. (The DAC voltages update simultaneously after the 32nd SCLK falling edge of the second write cycle). Reference is always powered-down (External reference must be used for proper operation).