ZHCS385D June   2013  – February 2024 CDCE913-Q1 , CDCEL913-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Configuration
      2. 8.3.2 Default Device Configuration
      3. 8.3.3 I2C Serial Interface
      4. 8.3.4 Data Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Hardware Interface
    5. 8.5 Programming
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread-Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Register Maps
    1. 10.1 I2C Configuration Registers
  12. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

PLL Frequency Planning

At a given input frequency (fIN), use Equation 1 to calculate the output frequency (fOUT) of the CDCE913-Q1 or CDCEL913-Q1 device.

Equation 1. GUID-53523C49-4B75-41C6-9B1A-02FDB5C45A5A-low.gif

where

  • M (1 to 511) and N (1 to 4095) are the multiplier or divider values of the PLL
  • Pdiv (1 to 127) is the output divider

Use Equation 2 to calculate the target VCO frequency (ƒVCO) of each PLL.

Equation 2. GUID-8402508A-4B2F-4503-AF6C-6F06236C15E3-low.gif

The PLL internally operates as fractional divider and requires the following multiplier or divider settings:

  • N
  • P = 4 – int(log2N / M); if P < 0 then P = 0
  • Q = int(N' / M)
  • R = N′ – M × Q

where

  • int(X) = integer portion of X
  • N′ = N × 2P
  • N ≥ M

80 MHz ≤ ƒVCO ≤ 230 MHz

16 ≤ Q ≤ 63 µs

0 ≤ P ≤ 4 µs

0 ≤ R ≤ 51 µs

Example:
for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2
fOUT = 54 MHzfOUT = 74.25 MHz
fVCO = 108 MHzfVCO = 148.50 MHz
P = 4 – int(log24) = 4 – 2 = 2P = 4 – int(log25.5) = 4 – 2 = 2
N' = 4 × 22 = 16N' = 11 × 22 = 44
Q = int(16) = 16Q = int(22) = 22
R = 16 – 16 = 0R = 44 – 44 = 0

The values for P, Q, R, and N' are automatically calculated when using TI Pro-Clock™ software.

The frequency of CLK1 shown in the application diagram can be obtained by passing the input frequency of the VCXO directly to output 1. The CLK2 frequency can be achieved by using the PLL constants derived in the first example. The value of CLK3 requires the same PLL constants as CLK2, but Pdiv3 is set to 1 instead of 2 to yield a frequency of 108 MHz.