SCAS882E June   2009  – October 2016 CDCE62002

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Thermal Information
    3. 7.3 Electrical Characteristics
    4. 7.4 Timing Requirements
    5. 7.5 SPI Bus Timing Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
      1. 9.2.1 Interface and Control Block
      2. 9.2.2 Input Block
      3. 9.2.3 Output Block
      4. 9.2.4 Synthesizer Block
      5. 9.2.5 Computing the Output Frequency
    3. 9.3 Feature Description
      1. 9.3.1 Phase Noise Analysis
      2. 9.3.2 Output-to-Output Isolationthe OUTPUT TO OUTPUT ISOLATION section
      3. 9.3.3 Device Control
      4. 9.3.4 External Control Pins
        1. 9.3.4.1 Factory Default Programming
      5. 9.3.5 Input Block
        1. 9.3.5.1 Reference Input Buffer
        2. 9.3.5.2 Smart Multiplexer Dividers
        3. 9.3.5.3 Auxiliary Input Port
        4. 9.3.5.4 Output Block
        5. 9.3.5.5 Synthesizer Block
        6. 9.3.5.6 Input Divider
        7. 9.3.5.7 Feedback and Feedback Bypass Divider
          1. 9.3.5.7.1 VCO Select
          2. 9.3.5.7.2 Prescaler
          3. 9.3.5.7.3 Loop Filter
        8. 9.3.5.8 Internal Loop Filter Component Configuration
      6. 9.3.6 Lock Detect
      7. 9.3.7 Crystal Input Interface
      8. 9.3.8 VCO Calibration
      9. 9.3.9 Start-Up Time Estimation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Generator
      2. 9.4.2 SERDES Start-Up and Clock Cleaner
      3. 9.4.3 Clocking ADCS With the CDCE62002
    5. 9.5 Programming
      1. 9.5.1 Interface and Control Block
        1. 9.5.1.1 SPI (Serial Peripheral Interface)
        2. 9.5.1.2 SPI Interface Master
        3. 9.5.1.3 SPI Consecutive Read/Write Cycles to the CDCE62002
        4. 9.5.1.4 Writing to the CDCE62002
        5. 9.5.1.5 Reading from the CDCE62002
        6. 9.5.1.6 Writing to EEPROM
        7. 9.5.1.7 CDCE62002 SPI Command Structure
      2. 9.5.2 Device Configuration
    6. 9.6 Register Maps
      1. 9.6.1 Device Registers: Register 0 Address 0x00
      2. 9.6.2 Device Registers: Register 1 Address 0x01
      3. 9.6.3 Device Registers: Register 2 Address 0x02
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package

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订购信息

1 Features

  • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter
  • Fully Configurable Outputs Including Frequency and Output Format
  • Smart Input Multiplexer Automatically Switches Between One of Two Reference Inputs
  • Multiple Operational Modes Include Clock Generation Through Crystal, SERDES Start-Up Mode, Jitter Cleaning, and Oscillator Based Holdover Mode
  • Integrated EEPROM Determines Device Configuration at Power Up
  • Excellent Jitter Performance
  • Integrated Frequency Synthesizer Including PLL, Multiple VCOs, and Loop Filter:
    • Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode
    • Programmable Charge Pump Gain and Loop Filter Settings
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz to 2.356 GHz.
  • Universal Output Blocks Support Up to 2 Differential, 4 Single-Ended, or Combinations of Differential or Single-Ended:
    • 0.5 ps RMS (10 kHz to 20 MHz) Output Jitter Performance
    • Low Output Phase Noise: –130 dBc/Hz at 1 MHz Offset, Fc = 491.52 MHz
    • Output Frequency Ranges From 10.94 MHz to 1.175 GHz in Synthesizer Mode
    • LVPECL, LVDS, and LVCMOS
    • Independent Output Dividers Support Divide Ratios for 1, 2, 3, 4, 5, 8, 10, 12, 16, 20, 24, and 32
  • Flexible Inputs With Innovative Smart Multiplexer:
    • Two Universal Differential Inputs Accept Frequencies from 1 MHz up to 500 MHz (LVPECL), 500 MHz (LVDS), or 250 MHz (LVCMOS)
    • One Auxiliary Input Accepts Crystals in the Range of 2 MHz to 42 MHz
    • Clock Generator Mode Using Crystal Input
    • Smart Input Multiplexer Can be Configured to Automatically Switch Between Highest Priority Clock Source Available Allowing for Fail-Safe Operation
  • Typical Power Consumption 750 mW at 3.3 V
  • Integrated EEPROM Stores Default Settings; Therefore, the Device Can Power Up in a Known, Predefined State
  • Offered in QFN-32 Package
  • ESD Protection Exceeds 2000 V HBM
  • Industrial Temperature Range: –40°C to +85°C

2 Applications

  • Data Converter and Data Aggregation Clocking
  • Wireless Infrastructure
  • Switches and Routers
  • Medical Electronics
  • Military and Aerospace
  • Industrial
  • Clock Generation and Jitter Cleaning

3 Description

The CDCE62002 device is a high-performance clock generator featuring low output jitter, a high degree of configurability through a SPI interface, and programmable start-up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5 ps RMS (1).

(1)10-kHz to 20-MHz integration bandwidth.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCE62002 VQFN (32) 5.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

CDCE62002 Application Example

CDCE62002 app_ex_cas882.gif

4 Revision History

Changes from D Revision (February 2012) to E Revision

  • Added figure cross references to Electrical TablesGo
  • Added figure titles.Go
  • Updated Figure 18Go
  • Updated Figure 20Go
  • Corrected description for bits 0 and 1 in CDCE62002 Register 0 Bit Definitions Go
  • Corrected the register bits for LVPECL-AC, LVPECL-DC, LVDS-AC, LVDS-DC reference inputs in Reference Input AC/DC Input Termination Table Go

Changes from C Revision (March 2011) to D Revision

  • Added 3 rows in TIMING REQUIREMENTS table, under Duty Cycle rowGo
  • Added a sentence below Equation 3Go
  • Changed last row last column in Figure 23 truth table from Disabled to Input Buffer Termination DisabledGo
  • Changed in Table 13, second column, 5th and 6th row from 1 to 0Go
  • Added a reference to Table 11 and 2 references to Table 12 in Table 6Go
  • Added 6 crossreferences to Table 8 Go
  • Changed changed last row in Table 8 Description column, from "always reads 1" to "May read back to 1 or 0"Go

Changes from B Revision (February 2010) to C Revision

  • Changed the description of Pin 30, REF_IN-.Go
  • Changed Pin 7 to open drain in Pin Functions tableGo
  • Changed the description of Pin 19, TESTSYNC To: Reserved Pin.....resistor.Go
  • Changed pin 31 From: Power To: A. Power in Pin Functions tableGo
  • Changed Pin Functions table, Pins 9, 12 to VCC_OUT0. Pins 13 and 16 to VCC_OUT1Go
  • Changed Note1 of the Pin Functions tableGo
  • Deleted Dividers and from ELEC CHARACTERISTICS table in row POFFGo
  • Changed Crytal input section first row From: Crystal Load Capacitance To: On-chip Load CapacitanceGo
  • Added SPI OUTPUT row From: PLL To: PLL_LOCKGo
  • Changed tr / tf Max value From: 735 To: 135Go
  • Deleted (Reg 0 RAM bit 9 = 1) and (Reg 0 RAM bit 9 = 0) from the TIMING REQUIREMENTS table Go
  • Added Driver Level and Max shunt capacitance to AUXILARY_IN REQUIREMENT in the TIMING REQUIREMENTS tableGo
  • Deleted Columns from Table 1: LVDS-HP and LVCMOS-HPGo
  • Changed Table 2 Go
  • Changed the OUTPUT TO OUTPUT ISOLATION sectionGo
  • Deleted the SPI CONTROL INTERFACE TIMING sectionGo
  • Updated Figure 18Go
  • Updated Reference Input Buffer Go
  • Updated Figure 20Go
  • Changed the Smart Multiplexer Dividers sectionGo
  • Changed Changed the text in the Smart Multiplexer Divider sectionGo
  • Changed Figure 24Go
  • Deleted column 3 db Corner C3R3 from Table 12Go
  • Added sections: VCO Calibration, Crystal Input Interface, and Startup TimeGo
  • Changed Figure 29Go
  • Changed the INTERFACE AND CONTROL BLOCK sectionGo
  • Changed figure Figure 36Go
  • Changed Table 17, RAM BITS To REGISTER BITSGo
  • Deleted the First four rows in Table 18 and the first columnGo
  • Deleted (6 settings+DisAble+Enable) in Register bit 19 of Table 18Go
  • Added ; set '0' to TI use Only in bit 26 in Table 18Go
  • Changed the description of bit 27 in Table 18Go
  • Deleted the First four rows in Table 19 and the first columnGo
  • Added Receiving Notification of Documentation Updates section Go

Changes from A Revision (July, 2009) to B Revision

  • Deleted feature reference to Single Ended Clock Source or Crystal and LVCMOS Input of up to 75 MHz Go
  • Deleted references to single ended inputs and CMOS clock from description.Go
  • Changed the description of Pin 2, AUX_INGo
  • Deleted LVCMOS INPUT MODE (AUX_IN) section from Electrical CharacteristicsGo
  • Changed Crystal Shunt Capacitance to Crystal Load Capacitance with a MIN value of 8Go
  • Deleted fREF – Single paramter from AUXILARY_IN_REQUIRMENTSGo
  • Deleted references to EEPROM Locking from "Interface and Control Block" sectionGo
  • Changed Auxiliary Input Port sectionGo
  • Deleted External Feed Back Mode sectionGo
  • Deleted External Feedback Option sectionGo
  • Changed EXTFEEDBACK to RESERVED for bit 10 in Table 16Go
  • Changed EELOCK to RESERVED for bit 30 in Table 18Go

Changes from * Revision (June 2009) to A Revision

  • Added information to Pin 18 description - The input has an internal 150-kΩ pull-up resistGo
  • Added NOTE: All VCC pins need to be connected for the device to operate properly.Go
  • Changed PLVPECL, PLVDS, PLVCMOS and POFF Unit values From: W To: mWGo
  • Deleted underscore before IN+Go
  • Deleted 6 from 8006Go
  • Changed Y4 to Y1Go
  • Added tr / tf MIN, TYP, and MAX valuesGo
  • Added (Reg 0 RAM bit 9 = 0) to fREF – Diff REF_DIV Go
  • Changed graphic input namingGo
  • Changed graphic input namingGo
  • Changed REF into REF_INGo
  • Changed graphicGo
  • Changed Table 4Go
  • Changed PDDRESET to PLLRESET, in Table 4Go
  • Changed Power_Down to PD, in Table 4Go
  • Changed PRI_IN to REF_IN in Figure 19Go
  • Changed PRI_IN to REF_INGo
  • Changed PRI_IN to REF_INGo
  • Changed part number errorGo
  • Changed REFERENCE to REF_IN and AUXILARY to AUX_IN, Table 16Go
  • Changed power to currentGo
  • Changed the description of bits 0 - 5 To: TI Test Registers. For TI Use Only in Table 19Go