ZHCSJ56C February 2018 – September 2019 BQ25882
PRODUCTION DATA.
REG15 is shown in Figure 58 and described in Table 30.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
Field | ADC_EN | ADC_RATE | ADC_SAMPLE[1:0] | RESERVED | RESERVED | RESERVED | RESERVED |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | ADC_EN | R/W | Yes | Yes | ADC Control:
0 – Disable ADC (default) 1 – Enable ADC |
|
6 | ADC_RATE | R/W | Yes | No | 0 – Continuous conversion (default)
1 – One-shot conversion |
|
5 | ADC_SAMPLE[1] | R/W | Yes | No | Sample Speed of ADC:
00 – 15-bit effective resolution 01 – 14-bit effective resolution 10 – 13-bit effective resolution 11 – 12-bit effective resolution (default) |
|
4 | ADC_SAMPLE[0] | R/W | Yes | No | ||
3 | RESERVED | R/W | Yes | No | Reserved bit always reads 0 | |
2 | RESERVED | R/W | Yes | No | Reserved bit always reads 0 | |
1 | RESERVED | R/W | Yes | No | Reserved bit always reads 0 | |
0 | RESERVED | R/W | Yes | No | Reserved bit always reads 0 |