ZHCSJ56C February   2018  – September 2019 BQ25882

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
      1.      Device Images
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  Device Power Up from Battery without Input Source
      3. 8.3.3  Device Power Up from Input Source
        1. 8.3.3.1 Poor Source Qualification
        2. 8.3.3.2 Input Source Type Detection
          1. 8.3.3.2.1 D+/D– Detection Sets Input Current Limit
          2. 8.3.3.2.2 Force Input Current Limit Detection
        3. 8.3.3.3 Power up REGN Regulator (LDO)
        4. 8.3.3.4 Converter Power Up
      4. 8.3.4  Input Current Optimizer (ICO)
      5. 8.3.5  Buck Mode Operation from Battery (OTG)
      6. 8.3.6  Power Path Management
        1. 8.3.6.1 Narrow VDC Architecture
        2. 8.3.6.2 Dynamic Power Management
        3. 8.3.6.3 Supplement Mode
      7. 8.3.7  Battery Charging Management
        1. 8.3.7.1 Autonomous Charging Cycle
        2. 8.3.7.2 Battery Charging Profile
        3. 8.3.7.3 Charging Termination
        4. 8.3.7.4 Thermistor Qualification
          1. 8.3.7.4.1 JEITA Guideline Compliance in Charge Mode
          2. 8.3.7.4.2 Cold/Hot Temperature Window in OTG Buck Mode
        5. 8.3.7.5 Charging Safety Timer
      8. 8.3.8  Integrated 16-Bit ADC for Monitoring
      9. 8.3.9  Status Outputs (PG, and INT)
        1. 8.3.9.1 Power Good Indicator (PG)
        2. 8.3.9.2 Interrupt to Host (INT)
      10. 8.3.10 Input Current Limit on ILIM Pin
      11. 8.3.11 Voltage and Current Monitoring
        1. 8.3.11.1 Voltage and Current Monitoring in Boost Mode
          1. 8.3.11.1.1 Input Over-voltage Protection
          2. 8.3.11.1.2 Input Under-Voltage Protection
          3. 8.3.11.1.3 System Over-Voltage Protection
          4. 8.3.11.1.4 System Over-Current Protection
        2. 8.3.11.2 Voltage and Current Monitoring in OTG Buck Mode
          1. 8.3.11.2.1 VBUS Over-Voltage Protection
          2. 8.3.11.2.2 VBUS Over-Current Protection
      12. 8.3.12 Thermal Regulation and Thermal Shutdown
        1. 8.3.12.1 Thermal Protection in Boost Mode
        2. 8.3.12.2 Thermal Protection in OTG Buck Mode
      13. 8.3.13 Battery Protection
        1. 8.3.13.1 Battery Overvoltage Protection (BATOVP)
        2. 8.3.13.2 Battery Over-Discharge Protection
      14. 8.3.14 Serial Interface
        1. 8.3.14.1 Data Validity
        2. 8.3.14.2 START and STOP Conditions
        3. 8.3.14.3 Byte Format
        4. 8.3.14.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.14.5 Slave Address and Data Direction Bit
        6. 8.3.14.6 Single Write and Read
        7. 8.3.14.7 Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
    5. 8.5 Register Maps
      1. 8.5.1  Battery Voltage Regulation Limit Register (Address = 00h) [reset = A0h]
        1. Table 9. REG00 Register Field Descriptions
      2. 8.5.2  Charger Current Limit Register (Address = 01h) [reset = 54h]
        1. Table 10. REG01 Register Field Descriptions
      3. 8.5.3  Input Voltage Limit Register (Address = 02h) [reset = 85h]
        1. Table 11. REG02 Register Field Descriptions
      4. 8.5.4  Input Current Limit Register (Address = 03h) [reset = 39h]
        1. Table 12. REG03 Register Field Descriptions
      5. 8.5.5  Precharge and Termination Current Limit Register (Address = 04h) [reset = 22h]
        1. Table 13. REG04 Register Field Descriptions
      6. 8.5.6  Charger Control 1 Register (Address = 05h) [reset = 9Dh]
        1. Table 14. REG05 Register Field Descriptions
      7. 8.5.7  Charger Control 2 Register (Address = 06h) [reset = 7Dh]
        1. Table 15. REG06 Register Field Descriptions
      8. 8.5.8  Charger Control 3 Register (Address = 07h) [reset = 0Ah]
        1. Table 16. REG07 Register Field Descriptions
      9. 8.5.9  Charger Control 4 Register (Address = 08h) [reset = 0Dh]
        1. Table 17. REG08 Register Field Descriptions
      10. 8.5.10 OTG Control Register (Address = 09h) [reset = F6h]
        1. Table 18. REG09 Register Field Descriptions
      11. 8.5.11 ICO Current Limit Register (Address = 0Ah) [reset = XXh]
        1. Table 19. REG0A Register Field Descriptions
      12. 8.5.12 Charger Status 1 Register (Address = 0Bh) [reset = XXh]
        1. Table 20. REG0B Register Field Descriptions
      13. 8.5.13 Charger Status 2 Register (Address = 0Ch) [reset = XXh]
        1. Table 21. REG0C Register Field Descriptions
      14. 8.5.14 NTC Status Register (Address = 0Dh) [reset = 0Xh]
        1. Table 22. REG0D Register Field Descriptions
      15. 8.5.15 FAULT Status Register (Address = 0Eh) [reset = XXh]
        1. Table 23. REG0E Register Field Descriptions
      16. 8.5.16 Charger Flag 1 Register (Address = 0Fh) [reset = 00h]
        1. Table 24. REG0F Register Field Descriptions
      17. 8.5.17 Charger Flag 2 Register (Address = 10h) [reset = 00h]
        1. Table 25. REG10 Register Field Descriptions
      18. 8.5.18 FAULT Flag Register (Address = 11h) [reset = 00h]
        1. Table 26. REG11 Register Field Descriptions
      19. 8.5.19 Charger Mask 1 Register (Address = 12h) [reset = 00h]
        1. Table 27. REG12 Register Field Descriptions
      20. 8.5.20 Charger Mask 2 Register (Address = 13h) [reset = 00h]
        1. Table 28. REG13 Register Field Descriptions
      21. 8.5.21 FAULT Mask Register (Address = 14h) [reset = 00h]
        1. Table 29. REG14 Register Field Descriptions
      22. 8.5.22 ADC Control Register (Address = 15h) [reset = 30h]
        1. Table 30. REG15 Register Field Descriptions
      23. 8.5.23 ADC Function Disable Register (Address = 16h) [reset = 00h]
        1. Table 31. REG16 Register Field Descriptions
      24. 8.5.24 IBUS ADC 1 Register (Address = 17h) [reset = 00h]
        1. Table 32. REG17 Register Field Descriptions
      25. 8.5.25 IBUS ADC 0 Register (Address = 18h) [reset = 00h]
        1. Table 33. REG18 Register Field Descriptions
      26. 8.5.26 ICHG ADC 1 Register (Address = 19h) [reset = 00h]
        1. Table 34. REG19 Register Field Descriptions
      27. 8.5.27 ICHG ADC 0 Register (Address = 1Ah) [reset = 00h]
        1. Table 35. REG1A Register Field Descriptions
      28. 8.5.28 VBUS ADC 1 Register (Address = 1Bh) [reset = 00h]
        1. Table 36. REG1B Register Field Descriptions
      29. 8.5.29 VBUS ADC 0 Register (Address = 1Ch) [reset = 00h]
        1. Table 37. REG1C Register Field Descriptions
      30. 8.5.30 VBAT ADC 1 Register (Address = 1Dh) [reset = 00h]
        1. Table 38. REG1D Register Field Descriptions
      31. 8.5.31 VBAT ADC 0 Register (Address = 1Eh) [reset = 00h]
        1. Table 39. REG1E Register Field Descriptions
      32. 8.5.32 VSYS ADC 1 Register (Address = 1Fh) [reset = 00h]
        1. Table 40. REG1F Register Field Descriptions
      33. 8.5.33 VSYS ADC 0 Register (Address = 20h) [reset = 00h]
        1. Table 41. REG20 Register Field Descriptions
      34. 8.5.34 TS ADC 1 Register (Address = 21h) [reset = 00h]
        1. Table 42. REG21 Register Field Descriptions
      35. 8.5.35 TS ADC 0 Register (Address = 22h) [reset = 00h]
        1. Table 43. REG22 Register Field Descriptions
      36. 8.5.36 TDIE ADC 1 Register (Address = 23h) [reset = 00h]
        1. Table 44. REG23 Register Field Descriptions
      37. 8.5.37 TDIE ADC 0 Register (Address = 24h) [reset = 00h]
        1. Table 45. REG24 Register Field Descriptions
      38. 8.5.38 Part Information Register (Address = 25h) [reset = 11h]
        1. Table 46. REG25 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input (VBUS / PMID) Capacitor
        3. 9.2.2.3 Output (VSYS) Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方产品免责声明
        1. 12.1.1.1 第三方产品免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

VVBUS_UVLOZ < VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENTS
IBAT Battery discharge current (BATP, BAT, SYS) VBAT = 9 V, No VBUS, SCL, SDA = 0 V or 1.8 V, ADC Disabled, TJ = 25℃ 11.5 14 µA
VBAT = 9 V, No VBUS, SCL, SDA = 0 V or 1.8 V, ADC Disabled, TJ < 85℃ 11.5 20 µA
IVBUS_HIZ Input supply current (VBUS) in HIZ VBUS = 5 V, High-Z Mode, no battery, ADC Disabled, TJ = 25℃ 30 35 µA
VBUS = 5 V, High-Z Mode, no battery, ADC Disabled, TJ < 85℃ 30 40 µA
IVBUS Input supply current (VBUS) VBUS = 5 V, VBAT = 7.6 V, converter not switching 1.5 3 mA
VBUS = 5 V, VBAT = 7.6 V, converter switching, ISYS = 0A 3 mA
IBAT_OTG Battery discharge current in OTG mode VBAT = 8.4 V, OTG Buck Mode,
IVBUS = 0A, converter switching		 3 mA
VBUS/VBAT POWER UP
VVBUS_OP VBUS operating range 3.9 6.2 V
VVBUS_UVLOZ VBUS rising for active I2C, no battery VBUS rising 3.3 3.6 V
VVBUS_PRESENT VBUS rising 3.65 3.9 V
VVBUS_OV VBUS over-voltage rising threshold VBUS rising 6.2 6.6 V
VBUS over-voltage falling threshold VBUS falling 5.9 6.4 V
VBAT_UVLOZ Battery for active I2C VBAT rising 3.7 4.0 4.335 V
VPOORSRC Bad adapter detection threshold 3.7 V
IPOORSRC Bad adapter detection current source 15 mA
POWER-PATH
VSYS Typical System Regulation Voltage ISYS = 0A, VBAT = 8.80 V > SYS_MIN[3:0], Charge Disabled (EN_CHG = 0). Offset above VBAT 100 mV
VSYS Typical System Regulation Voltage ISYS = 0A, VBAT < SYS_MIN[3:0], Charge Disabled (EN_CHG = 0). Offset above SYS_MIN 200 mV
VSYS_MIN System Regulation Voltage VBAT < SYS_MIN[3:0] = 1010, Charge Disabled (EN_CHG = 0) 7 7.2 V
RON_QBLK (Q1) Blocking MOSFET on-resistance between VBUS and PMID (QB) TJ = 25°C 25 36 mΩ
TJ = – 40°C - 125°C 25 52 mΩ
RON_QHS (Q2) High-side switching MOSFET on-resistance between SW and SYS (Q2) TJ = 25°C 30 40 mΩ
TJ = – 40°C - 125°C 30 55 mΩ
RON_QLS (Q3) Low-side switching MOSFET on-resistance between SW and GND (Q3) TJ = 25°C 40 59 mΩ
TJ = – 40°C - 125°C 40 80 mΩ
BATTERY CHARGER
VREG_RANGE Typical charge voltage regulation range 6.8 9.2 V
VREG_STEP Typical charge voltage step 10 mV
VREG_ACC Charge voltage accuracy VREG = 8.40 V, TJ = – 40°C - 85°C 8.3664 8.4 8.4336 V
VREG = 8.70 V, TJ = – 40°C - 85°C 8.6652 8.7 8.7348 V
VREG = 8.80 V, TJ = – 40°C - 85°C 8.7648 8.8 8.8352 V
ICHG_RANGE Charge current regulation range 0 2200 mA
ICHG_STEP Charge current regulation step 50 mA
ICHG_ACC Fast Charge current regulation accuracy ICHG = 250 mA, VBAT = 6.2 V or 7.6 V, TJ = – 20°C - 85°C -25 25 %
ICHG = 500 mA, VBAT = 6.2 V or 7.6 V, TJ = – 20°C - 85°C -10 10 %
ICHG = 1000 mA, VBAT = 6.2 V or 7.6 V, TJ = – 20°C - 85°C -7.5 7.5 %
IPRECHG_RANGE Precharge current range 50 800 mA
IPRECHG_STEP Typical precharge current step 50 mA
IPRECHG_ACC Precharge current accuracy VBAT = 5.2 V, IPRECHG = 200 mA,
TJ = – 20°C - 85°C		 -20 20 %
ITERM_RANGE Termination current range 50 800 mA
ITERM_STEP Typical termination current step 50 mA
ITERM_ACC Termination current accuracy ICHG = 1.5A, ITERM = 50 mA,
TJ = – 40°C - 85°C		 -40 40 %
ICHG = 1.5A, ITERM = 150 mA,
TJ = – 40°C - 85°C		 -20 20 %
VBAT_SHORT Short Battery Voltage rising threshold to start pre-charging VBAT rising 4.1 4.4 4.7 V
VBAT_SHORT_HYS Short Battery Voltage falling threshold to stop pre-charging VBAT falling 3.7 4.0 4.3 V
IBAT_SHORT Short Battery Voltage trickle charging current VBAT < 4.4 V 100 mA
VBAT_LOWV VBAT LOWV Rising threshold to start fast-charging VBAT rising, VBATLOW = 6.0 V 5.7 6 6.3 V
VBAT LOWV Falling threshold to stop fast-charging VBAT falling, VBATLOW = 6.0 V 5.3 5.6 5.9 V
VRECHG Recharge threshold below VREG VBAT falling, VRECHG[1:0] = 01 200 mV
VBAT falling, VRECHG[1:0] = 10 300 mV
RON_QBAT (Q4) MOSFET on-resistance between SYS and BAT (Q4) TJ = 25°C 15 18 mΩ
TJ = – 40°C - 125°C 15 26 mΩ
RBATP BATP Input resistance VBAT = 8 V, VBUS = 5 V, EN_HIZ = 1, ADC Disabled 2.7 MΩ
RBATN BATN Input resistance VBAT = 8 V, VBUS = 5 V, EN_HIZ = 1, ADC Disabled 2.7 MΩ
INPUT VOLTAGE / CURRENT REGULATION
VINDPM_RANGE Input voltage regulation range 3.9 5.5 V
VINDPM_STEP Input voltage regulation step 100 mV
VINDPM Input voltage limit VINDPM = 3.9 V 3.783 3.9 4.017 V
VINDPM = 4.4 V 4.268 4.4 4.532 V
IINDPM_RANGE Input current regulation range 500 3300 mA
IINDPM_STEP Input current regulation step 100 mA
IINDPM_ACC Input current regulation limit IINDPM = 500 mA 445 470 500 mA
IINDPM = 900 mA 765 832.5 900 mA
IINDPM = 2500 mA 2125 2312.5 2500 mA
IINDPM = 3000 mA 2550 2775 3000 mA
KILIM IINMAX = KILIM/RILIM, Input Current regulation by ILIM pin = 1.5A 1000 1085 1170 A x Ω
D+/D- DETECTION
VD+D-_600MVSRC D+/D- Voltage Source (600 mV) 500 600 700 mV
ID+_10UASRC D+ Current Source (10 µA) 7 10 14 µA
ID+D-_100UASNK D+/D- Current Sink (100 µA) 50 100 150 µA
VD+D-_0P325 D+/D- Comparator Threshold for Secondary Detection 250 400 mV
VD+_0P8 D+Comparator Threshold for Data Contact Detection 800 mV
RD-_19K D- Resistor to Ground (19 kΩ) 14.25 24.8 kΩ
VD+D-_1P2 D+/D- Threshold for Non-standard adapter 1.05 1.35 V
VD+D-_2P0 D+/D- Threshold for Non-standard adapter 1.85 2.15 V
VD+D-_2P8 D+/D- Threshold for Non-standard adapter 2.55 2.85 V
ID+D-_LKG D+/D- Leakage Current HiZ -1 1 µA
BATTERY OVER-VOLTAGE PROTECTION
VBAT_OVP Battery over-voltage rising threshold VBAT rising, as percentage of VREG 103 104 105 %
Battery over-voltage falling threshold VBAT falling, as percentage of VREG 101 102 103 %
THERMAL REGULATION AND THERMAL SHUTDOWN
TREG Junction temperature regulation accuracy TREG = 120°C 120 °C
TSHUT Thermal Shutdown Rising threshold Temperature Increasing 150 °C
Thermal Shutdown Falling threshold Temperature Decreasing 120 °C
JEITA THERMISTOR COMPARATOR (BOOST MODE)
VT1 T1 (0°C) threshold, Charge suspended below this temperature. As Percentage to REGN 72.75 73.25 73.75 %
VT1_HYS Charge re-enabled to ICHG/2 and VREG above this temperature As Percentage to REGN 1.3 %
VT2 T2 (10°C) threshold, Charge back to ICHG/2 and VREG below this temperature As Percentage to REGN 67.75 68.25 68.75 %
VT2_HYS Charge back to ICHG and VREG above this temperature As Percentage to REGN 1.3 %
VT3 T3 (45°C) threshold, Charge back to ICHG and 8.1 V above this temperature. As Percentage to REGN 44.25 44.75 45.25 %
VT3_HYS Charge back to ICHG and VREG below this temperature As Percentage to REGN 1 %
VT5 T5 (60°C) threshold, charge suspended above this temperature. As Percentage to REGN 33.875 34.375 34.875 %
VT5_HYS Charge back to ICHG and 8.1 V below this temperature As Percentage to REGN 1.3 %
COLD/HOT THERMISTOR COMPARATOR (OTG BUCK MODE)
VBCOLD0 Cold Temperature Threshold 0, TS pin Voltage Rising Threshold As Percentage to REGN, BCOLD = 0 (Approx. – 10°C w/ 103AT) 76.5 77 77.5 %
VBCOLD0_HYS Cold Temperature Threshold 0, TS pin Voltage Falling Threshold As Percentage to REGN 1 %
VBCOLD1 Cold Temperature Threshold 1, TS pin Voltage Rising Threshold As Percentage to REGN, BCOLD = 1 (Approx. – 20°C w/ 103AT) 79.5 80 80.5 %
VBCOLD1_HYS Cold Temperature Threshold 1, TS pin Voltage Falling Threshold As Percentage to REGN 1 %
VBHOT0 Hot Temperature Threshold 0, TS pin Voltage Falling Threshold As Percentage to REGN, BHOT[1:0] = 01 (Approx. 55°C w/ 103AT) 37.25 37.75 38.25 %
VBHOT0_HYS Hot Temperature Threshold 0, TS pin Voltage Rising Threshold As Percentage to REGN 3 %
VBHOT1 Hot Temperature Threshold 1, TS pin Voltage falling Threshold As Percentage to REGN, BHOT[1:0] = 00 (Approx. 60°C w/ 103AT) 33.875 34.375 34.875 %
VBHOT1_HYS Hot Temperature Threshold 1, TS pin Voltage rising Threshold As Percentage to REGN 3 %
VBHOT2 Hot Temperature Threshold 2, TS pin Voltage falling Threshold As Percentage to REGN, BHOT[1:0] = 10 (Approx. 65°C w/ 103AT) 30.75 31.25 31.75 %
VBHOT1_HY2 Hot Temperature Threshold 2, TS pin Voltage rising Threshold As Percentage to REGN 3 %
BOOST MODE CONVERTER
FSW PWM switching frequency Oscillator frequency 1.35 1.5 1.65 MHz
OTG BUCK MODE CONVERTER
VOTG_BAT Battery voltage exiting OTG mode BAT falling 5.85 6 6.15 V
VOTG_RANGE Typical OTG Buck mode voltage regulation range 4.5 5.5 V
VOTG_STEP Typical OTG Buck mode voltage regulation step 100 mV
VOTG_ACC OTG Buck mode voltage regulation accuracy IVBUS = 0A, OTG_VLIM = 5 V -3 3 %
IOTG_RANGE Typical OTG Buck mode current regulation range 0.5 2 A
IOTG_STEP Typical OTG Buck mode current regulation step 100 mA
IOTG_ACC OTG Buck mode current regulation accuracy OTG_ILIM = 1A -15 -7.5 0.05 %
VOTG_OVP OTG Buck mode over-voltage threshold 5.8 6 V
REGN LDO
VREGN REGN LDO output voltage VVBUS = 5 V, IREGN = 20 mA 4.7 4.8 V
IREGN REGN LDO current limit VVBUS = 5 V, VREGN = 3.8 V 50 mA
Analog-to-Digital Converter (ADC)
tADC_CONV Conversion time, each measurement ADC_SAMPLE[1:0] = 00 24 ms
ADC_SAMPLE[1:0] = 01 12 ms
ADC_SAMPLE[1:0] = 10 6 ms
ADC_SAMPLE[1:0] = 11 3 ms
ADCRES Effective resolution ADC_SAMPLE[1:0] = 00 14 15 bits
ADC_SAMPLE[1:0] = 01 13 14 bits
ADC_SAMPLE[1:0] = 10 12 13 bits
ADC_SAMPLE[1:0] = 11 10 11 bits
ADC MEASUREMENT RANGES AND LSB
IBUS_ADC_RANGE ADC BUS current range 0 4 A
IBUS_ADC_LSB ADC BUS current LSB 1 mA
IBAT_ADC_RANGE ADC BAT current range 0 4 A
IBAT_ADC_LSB ADC BAT current LSB 1 mA
VBUS_ADC_RANGE ADC BUS voltage range 0 6.5 V
VBUS_ADC_LSB ADC BUS voltage LSB 1 mV
VSYS_ADC_RANGE ADC SYS voltage range 0 10 V
VSYS_ADC_LSB ADC SYS voltage LSB 1 mV
VBAT_ADC_RANGE ADC BAT voltage range 0 10 V
VBAT_ADC_LSB ADC BAT voltage LSB 1 mV
VTS_ADC_RANGE ADC TS voltage range 20 80 %
VTS_ADC_LSB ADC TS voltage LSB 0.098 %
VTDIE_ADC_RANGE ADC Die temperature range 0 150 °C
VTDIE_ADC_LSB ADC Die temperature LSB 1 °C
I2C INTERFACE (SCL, SDA)
VIH Input high threshold level, SDA and SCL Pull-up rail 1.8 V 1.3 V
VIL Input low threshold level Pull-up rail 1.8 V 0.4 V
VOL Output low threshold level Sink current = 5 mA 0.4 V
IBIAS High level leakage current Pull-up rail 1.8 V 1 µA
LOGIC I/O PIN (/CE, PSEL)
VIH Input high threshold level 1.3 V
VIL Input low threshold level 0.4 V
IIN_BIAS High level leakage current Pull-up rail 1.8 V 1 µA
LOGIC O PIN (/INT, /PG, STAT)
VOL Output low threshold level Sink current = 5 mA 0.4 V
IOUT_BIAS High level leakage current Pull-up rail 1.8 V 1 µA