ZHCSIM5F December   2016  – July 2018 AM5746 , AM5748 , AM5749

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
    2. 3.2 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  EMIF
      5. 4.3.5  GPMC
      6. 4.3.6  Timer
      7. 4.3.7  I2C
      8. 4.3.8  HDQ1W
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 Test Interfaces
      25. 4.3.25 System and Miscellaneous
        1. 4.3.25.1 Sysboot
        2. 4.3.25.2 PRCM
        3. 4.3.25.3 RTC
        4. 4.3.25.4 SDMA
        5. 4.3.25.5 INTC
        6. 4.3.25.6 Observability
        7. 4.3.25.7 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH) Limits
      1. Table 5-1 Power-On Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-7  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-8  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-9  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-11 LVCMOS OSC Buffers DC Electrical Characteristics
      6. Table 5-12 BC1833IHHV Buffers DC Electrical Characteristics
      7. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      HDMIPHY DC Electrical Characteristics
      10. 5.7.2      USBPHY DC Electrical Characteristics
      11. 5.7.3      SATAPHY DC Electrical Characteristics
      12. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RTC Oscillator Input Clock
            1. 5.10.4.1.4.1 RTC Oscillator External Crystal
            2. 5.10.4.1.4.2 RTC Oscillator Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  I2C
          1. Table 5-64 Timing Requirements for I2C Input Timings
          2. Table 5-65 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-66 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        9. 5.10.6.9  HDQ1W
          1. 5.10.6.9.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.9.2 HDQ/1-Wire—1-Wire Mode
        10. 5.10.6.10 UART
          1. Table 5-71 Timing Requirements for UART
          2. Table 5-72 Switching Characteristics Over Recommended Operating Conditions for UART
        11. 5.10.6.11 McSPI
        12. 5.10.6.12 QSPI
        13. 5.10.6.13 McASP
          1. Table 5-79 Timing Requirements for McASP1
          2. Table 5-80 Timing Requirements for McASP2
          3. Table 5-81 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-82 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-83 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-84 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        14. 5.10.6.14 USB
          1. 5.10.6.14.1 USB1 DRD PHY
          2. 5.10.6.14.2 USB2 PHY
        15. 5.10.6.15 SATA
        16. 5.10.6.16 PCIe
        17. 5.10.6.17 CAN
          1. 5.10.6.17.1 DCAN
          2. 5.10.6.17.2 MCAN-FD
          3. Table 5-96  Timing Requirements for CANx Receive
          4. Table 5-97  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        18. 5.10.6.18 GMAC_SW
          1. 5.10.6.18.1 GMAC MII Timings
            1. Table 5-98  Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-99  Timing Requirements for miin_txclk - MII Operation
            3. Table 5-100 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-101 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.18.2 GMAC MDIO Interface Timings
          3. 5.10.6.18.3 GMAC RMII Timings
            1. Table 5-106 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-107 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-108 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-109 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.18.4 GMAC RGMII Timings
            1. Table 5-113 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-114 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-115 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-116 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        19. 5.10.6.19 eMMC/SD/SDIO
          1. 5.10.6.19.1 MMC1—SD Card Interface
            1. 5.10.6.19.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.19.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.19.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.19.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.19.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.19.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.19.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.19.2 MMC2 — eMMC
            1. 5.10.6.19.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.19.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.19.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.19.2.4 High-speed JC64 DDR, 8-bit data
          3. 5.10.6.19.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.19.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.19.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.19.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.19.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.19.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        20. 5.10.6.20 PRU-ICSS
          1. 5.10.6.20.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.20.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-165 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-166 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.20.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.20.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-168 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-169 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.20.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-170 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-171 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-172 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.20.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.20.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-175 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-176 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-177 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.20.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.20.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-178 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-179 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-180 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.20.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-181 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-183 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-184 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.20.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-185 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-186 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.20.5 PRU-ICSS IOSETs
          6. 5.10.6.20.6 PRU-ICSS Manual Functional Mapping
        21. 5.10.6.21 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-209 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-210 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-211 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-212 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 TPIU
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IVA
    6. 6.6  EVE
    7. 6.7  IPU
    8. 6.8  VPE
    9. 6.9  GPU
    10. 6.10 PRU-ICSS
    11. 6.11 Memory Subsystem
      1. 6.11.1 EMIF
      2. 6.11.2 GPMC
      3. 6.11.3 ELM
      4. 6.11.4 OCMC
    12. 6.12 Interprocessor Communication
      1. 6.12.1 Mailbox
      2. 6.12.2 Spinlock
    13. 6.13 Interrupt Controller
    14. 6.14 EDMA
    15. 6.15 Peripherals
      1. 6.15.1  VIP
      2. 6.15.2  DSS
      3. 6.15.3  Timers
      4. 6.15.4  I2C
      5. 6.15.5  HDQ1W
      6. 6.15.6  UART
        1. 6.15.6.1 UART Features
        2. 6.15.6.2 IrDA Features
        3. 6.15.6.3 CIR Features
      7. 6.15.7  McSPI
      8. 6.15.8  QSPI
      9. 6.15.9  McASP
      10. 6.15.10 USB
      11. 6.15.11 SATA
      12. 6.15.12 PCIe
      13. 6.15.13 CAN
        1. 6.15.13.1 DCAN
        2. 6.15.13.2 MCAN-FD
      14. 6.15.14 GMAC_SW
      15. 6.15.15 eMMC/SD/SDIO
      16. 6.15.16 GPIO
      17. 6.15.17 ePWM
      18. 6.15.18 eCAP
      19. 6.15.19 eQEP
    16. 6.16 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Power Supply Mapping
    2. 7.2 DDR3 Board Design and Layout Guidelines
      1. 7.2.1 DDR3 General Board Layout Guidelines
      2. 7.2.2 DDR3 Board Design and Layout Guidelines
        1. 7.2.2.1  Board Designs
        2. 7.2.2.2  DDR3 EMIFs
        3. 7.2.2.3  DDR3 Device Combinations
        4. 7.2.2.4  DDR3 Interface Schematic
          1. 7.2.2.4.1 32-Bit DDR3 Interface
          2. 7.2.2.4.2 16-Bit DDR3 Interface
        5. 7.2.2.5  Compatible JEDEC DDR3 Devices
        6. 7.2.2.6  PCB Stackup
        7. 7.2.2.7  Placement
        8. 7.2.2.8  DDR3 Keepout Region
        9. 7.2.2.9  Bulk Bypass Capacitors
        10. 7.2.2.10 High-Speed Bypass Capacitors
          1. 7.2.2.10.1 Return Current Bypass Capacitors
        11. 7.2.2.11 Net Classes
        12. 7.2.2.12 DDR3 Signal Termination
        13. 7.2.2.13 VREF_DDR Routing
        14. 7.2.2.14 VTT
        15. 7.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.2.2.15.1 Four DDR3 Devices
            1. 7.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.2.2.15.2 Two DDR3 Devices
            1. 7.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.2.2.15.3 One DDR3 Device
            1. 7.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.2.2.16 Data Topologies and Routing Definition
          1. 7.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.2.2.17 Routing Specification
          1. 7.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.2.2.17.2 DQS and DQ Routing Specification
    3. 7.3 High Speed Differential Signal Routing Guidance
    4. 7.4 Power Distribution Network Implementation Guidance
    5. 7.5 Thermal Solution Guidance
    6. 7.6 Single-Ended Interfaces
      1. 7.6.1 General Routing Guidelines
      2. 7.6.2 QSPI Board Design and Layout Guidelines
    7. 7.7 LJCB_REFN/P Connections
    8. 7.8 Clock Routing Guidelines
      1. 7.8.1 32-kHz Oscillator Routing
      2. 7.8.2 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1  Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2  Tools and Software
    3. 8.3  Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4  Receiving Notification of Documentation Updates
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  商标
    8. 8.8  静电放电警告
    9. 8.9  Export Control Notice
    10. 8.10 术语表
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Mechanical Data

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABZ|760
散热焊盘机械数据 (封装 | 引脚)
订购信息

1.1 特性

  • Arm® Cortex®-A15 双核微处理器子系统
  • 多达两个 C66x 浮点 VLIW DSP
    • 对象代码与 C67x 和 C64x+ 完全兼容
    • 每周期最多 32 次 16 × 16 位定点乘法
  • 片上 L3 RAM 高达 2.5MB
  • 两个 DDR3/DDR3L 存储器接口 (EMIF) 模块
    • 最高支持 DDR3-1333 速率
    • 每个 EMIF 支持高达 2GB
    • 在主要 EMIF 上支持 ECC
  • 2 个双核 Arm®Cortex®-M4 协处理器（IPU1 和 IPU2）
  • 多达 2 个嵌入式视觉引擎 (EVE)
  • IVA-HD 子系统
    • 针对 H.264 编解码器的 4K @ 15fps 编码和解码支持
    • 其他编解码器高达 1080p60
  • 显示子系统
    • 全高清视频（1920 × 1080p，60fps）
    • 多个视频输入和视频输出
    • 2D 和 3D 图形
    • 具有 DMA 引擎和多达 3 条管线的显示控制器
    • HDMI™编码器：兼容 HDMI 1.4a 和 DVI 1.0
  • 2 个双核可编程实时单元和工业通信子系统 (PRU-ICSS)
  • 2D 图形加速器 (BB2D) 子系统
    • Vivante®GC320 内核
  • 视频处理引擎 (VPE)
  • 双核 PowerVR®SGX544 3D GPU
  • 安全引导支持
    • 硬件强制可信根
    • 客户可编程的秘钥和 OTP 数据
    • 支持接管保护、IP 保护和防回滚保护
  • 加密加速支持
    • 支持加密内核
      • AES – 128/192/256 位秘钥大小
      • 3DES – 56/112/168 位秘钥大小
      • MD5、SHA1
      • SHA2 – 224/256/384/512
      • 真随机数生成器
    • DMA 支持
  • 调试安全
    • 安全软件控制的调试访问
    • 安全感知调试
  • 可信执行环境 (TEE) 支持
    • 基于 Arm TrustZone 的 TEE
    • 可实现隔离的广泛防火墙支持
    • 安全 DMA 路径和互联
    • 安全监视器/计时器/IPC
  • 2 个视频输入端口 (VIP) 模块
    • 支持多达 8 个多路复用输入端口
  • 通用存储器控制器 (GPMC)
  • 增强型直接存储器存取 (EDMA) 控制器
  • 2 端口千兆以太网 (GMAC)
  • 16 个 32 位通用定时器
  • 32 位 MPU 看门狗定时器
  • 5 个内部集成电路 (I2C) 端口
  • HDQ™/单线 ®接口
  • 10 个可配置 UART/IrDA/CIR 模块
  • 4 个多通道串行外设接口 (McSPI)
  • 四路 SPI 接口 (QSPI)
  • 第 2 代 SATA 接口
  • 8 个多通道音频串行端口 (McASP) 模块
  • 超高速 USB 3.0 双角色设备
  • 高速 USB 2.0 双角色设备
  • 四个多媒体卡/安全数字/安全数字输入输出接口 (MMC™/SD™/SDIO)
  • 带有两个 5Gbps 通道的 PCI Express®3.0 子系统
    • 1 个与第 2 代兼容的双通道端口
    • 或 2 个与第 2 代兼容的单通道端口
  • 多达 2 个控制器局域网 (DCAN) 模块
    • CAN 2.0B 协议
  • 模块化控制器局域网 (MCAN) 模块
    • CAN 2.0B 协议，具有 FD（灵活数据速率）功能
  • 多达 247 个通用型 I/O (GPIO) 引脚
  • 电源、复位和时钟管理
  • 片上调试，采用 CTool 技术
  • 28nm CMOS 技术
  • 23mm × 23mm、0.8mm 间距、760 引脚 BGA (ABZ)