ZHCSIM5F December   2016  – July 2018 AM5746 , AM5748 , AM5749

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
    2. 3.2 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  EMIF
      5. 4.3.5  GPMC
      6. 4.3.6  Timer
      7. 4.3.7  I2C
      8. 4.3.8  HDQ1W
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 Test Interfaces
      25. 4.3.25 System and Miscellaneous
        1. 4.3.25.1 Sysboot
        2. 4.3.25.2 PRCM
        3. 4.3.25.3 RTC
        4. 4.3.25.4 SDMA
        5. 4.3.25.5 INTC
        6. 4.3.25.6 Observability
        7. 4.3.25.7 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH) Limits
      1. Table 5-1 Power-On Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-7  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-8  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-9  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-11 LVCMOS OSC Buffers DC Electrical Characteristics
      6. Table 5-12 BC1833IHHV Buffers DC Electrical Characteristics
      7. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      HDMIPHY DC Electrical Characteristics
      10. 5.7.2      USBPHY DC Electrical Characteristics
      11. 5.7.3      SATAPHY DC Electrical Characteristics
      12. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RTC Oscillator Input Clock
            1. 5.10.4.1.4.1 RTC Oscillator External Crystal
            2. 5.10.4.1.4.2 RTC Oscillator Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  I2C
          1. Table 5-64 Timing Requirements for I2C Input Timings
          2. Table 5-65 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-66 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        9. 5.10.6.9  HDQ1W
          1. 5.10.6.9.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.9.2 HDQ/1-Wire—1-Wire Mode
        10. 5.10.6.10 UART
          1. Table 5-71 Timing Requirements for UART
          2. Table 5-72 Switching Characteristics Over Recommended Operating Conditions for UART
        11. 5.10.6.11 McSPI
        12. 5.10.6.12 QSPI
        13. 5.10.6.13 McASP
          1. Table 5-79 Timing Requirements for McASP1
          2. Table 5-80 Timing Requirements for McASP2
          3. Table 5-81 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-82 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-83 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-84 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        14. 5.10.6.14 USB
          1. 5.10.6.14.1 USB1 DRD PHY
          2. 5.10.6.14.2 USB2 PHY
        15. 5.10.6.15 SATA
        16. 5.10.6.16 PCIe
        17. 5.10.6.17 CAN
          1. 5.10.6.17.1 DCAN
          2. 5.10.6.17.2 MCAN-FD
          3. Table 5-96  Timing Requirements for CANx Receive
          4. Table 5-97  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        18. 5.10.6.18 GMAC_SW
          1. 5.10.6.18.1 GMAC MII Timings
            1. Table 5-98  Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-99  Timing Requirements for miin_txclk - MII Operation
            3. Table 5-100 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-101 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.18.2 GMAC MDIO Interface Timings
          3. 5.10.6.18.3 GMAC RMII Timings
            1. Table 5-106 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-107 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-108 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-109 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.18.4 GMAC RGMII Timings
            1. Table 5-113 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-114 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-115 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-116 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        19. 5.10.6.19 eMMC/SD/SDIO
          1. 5.10.6.19.1 MMC1—SD Card Interface
            1. 5.10.6.19.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.19.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.19.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.19.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.19.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.19.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.19.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.19.2 MMC2 — eMMC
            1. 5.10.6.19.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.19.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.19.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.19.2.4 High-speed JC64 DDR, 8-bit data
          3. 5.10.6.19.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.19.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.19.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.19.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.19.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.19.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        20. 5.10.6.20 PRU-ICSS
          1. 5.10.6.20.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.20.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-165 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-166 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.20.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-167 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.20.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-168 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-169 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.20.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-170 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-171 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-172 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.20.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.20.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-173 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-174 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-175 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-176 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-177 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.20.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.20.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-178 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-179 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-180 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.20.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-181 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-182 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-183 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-184 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.20.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-185 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-186 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.20.5 PRU-ICSS IOSETs
          6. 5.10.6.20.6 PRU-ICSS Manual Functional Mapping
        21. 5.10.6.21 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-209 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-210 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-211 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-212 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 TPIU
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  IVA
    6. 6.6  EVE
    7. 6.7  IPU
    8. 6.8  VPE
    9. 6.9  GPU
    10. 6.10 PRU-ICSS
    11. 6.11 Memory Subsystem
      1. 6.11.1 EMIF
      2. 6.11.2 GPMC
      3. 6.11.3 ELM
      4. 6.11.4 OCMC
    12. 6.12 Interprocessor Communication
      1. 6.12.1 Mailbox
      2. 6.12.2 Spinlock
    13. 6.13 Interrupt Controller
    14. 6.14 EDMA
    15. 6.15 Peripherals
      1. 6.15.1  VIP
      2. 6.15.2  DSS
      3. 6.15.3  Timers
      4. 6.15.4  I2C
      5. 6.15.5  HDQ1W
      6. 6.15.6  UART
        1. 6.15.6.1 UART Features
        2. 6.15.6.2 IrDA Features
        3. 6.15.6.3 CIR Features
      7. 6.15.7  McSPI
      8. 6.15.8  QSPI
      9. 6.15.9  McASP
      10. 6.15.10 USB
      11. 6.15.11 SATA
      12. 6.15.12 PCIe
      13. 6.15.13 CAN
        1. 6.15.13.1 DCAN
        2. 6.15.13.2 MCAN-FD
      14. 6.15.14 GMAC_SW
      15. 6.15.15 eMMC/SD/SDIO
      16. 6.15.16 GPIO
      17. 6.15.17 ePWM
      18. 6.15.18 eCAP
      19. 6.15.19 eQEP
    16. 6.16 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Power Supply Mapping
    2. 7.2 DDR3 Board Design and Layout Guidelines
      1. 7.2.1 DDR3 General Board Layout Guidelines
      2. 7.2.2 DDR3 Board Design and Layout Guidelines
        1. 7.2.2.1  Board Designs
        2. 7.2.2.2  DDR3 EMIFs
        3. 7.2.2.3  DDR3 Device Combinations
        4. 7.2.2.4  DDR3 Interface Schematic
          1. 7.2.2.4.1 32-Bit DDR3 Interface
          2. 7.2.2.4.2 16-Bit DDR3 Interface
        5. 7.2.2.5  Compatible JEDEC DDR3 Devices
        6. 7.2.2.6  PCB Stackup
        7. 7.2.2.7  Placement
        8. 7.2.2.8  DDR3 Keepout Region
        9. 7.2.2.9  Bulk Bypass Capacitors
        10. 7.2.2.10 High-Speed Bypass Capacitors
          1. 7.2.2.10.1 Return Current Bypass Capacitors
        11. 7.2.2.11 Net Classes
        12. 7.2.2.12 DDR3 Signal Termination
        13. 7.2.2.13 VREF_DDR Routing
        14. 7.2.2.14 VTT
        15. 7.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.2.2.15.1 Four DDR3 Devices
            1. 7.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.2.2.15.2 Two DDR3 Devices
            1. 7.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.2.2.15.3 One DDR3 Device
            1. 7.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.2.2.16 Data Topologies and Routing Definition
          1. 7.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.2.2.17 Routing Specification
          1. 7.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.2.2.17.2 DQS and DQ Routing Specification
    3. 7.3 High Speed Differential Signal Routing Guidance
    4. 7.4 Power Distribution Network Implementation Guidance
    5. 7.5 Thermal Solution Guidance
    6. 7.6 Single-Ended Interfaces
      1. 7.6.1 General Routing Guidelines
      2. 7.6.2 QSPI Board Design and Layout Guidelines
    7. 7.7 LJCB_REFN/P Connections
    8. 7.8 Clock Routing Guidelines
      1. 7.8.1 32-kHz Oscillator Routing
      2. 7.8.2 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1  Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2  Tools and Software
    3. 8.3  Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4  Receiving Notification of Documentation Updates
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  商标
    8. 8.8  静电放电警告
    9. 8.9  Export Control Notice
    10. 8.10 术语表
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Mechanical Data

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABZ|760
散热焊盘机械数据 (封装 | 引脚)
订购信息

QSPI

The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to external SPI devices. This module has a memory mapped register interface, which provides a direct interface for accessing data from external SPI devices and thus simplifying software requirements. It works as a master only. There is one QSPI module in the device and it is primary intended for fast booting from quad-SPI flash memories.

General SPI features:

  • Programmable clock divider
  • Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
  • 4 external chip select signals
  • Support for 3-, 4- or 6-pin SPI interface
  • Programmable CS_N to DOUT delay from 0 to 3 DCLKs
  • Programmable signal polarities
  • Programmable active clock edge
  • Software controllable interface allowing for any type of SPI transfer

NOTE

For more information, see the Quad Serial Peripheral Interface section of the Device TRM.

CAUTION

The IO Timings provided in this section are only valid for some QSPI usage modes when the corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables found in this section.

CAUTION

The IO Timings provided in this section are only valid when all QSPI Chip Selects used in a system are configured to use the same Clock Mode (either Clock Mode 0 or Clock Mode3).

Table 5-76 and Table 5-77 present Timing and Switching Characteristics for Quad SPI Interface.

Table 5-76 Switching Characteristics for QSPI

No PARAMETER DESCRIPTION Mode MIN MAX UNIT
Q1 tc(SCLK) Cycle time, sclk Manual IO Timing Modes, Clock Mode 0 10.41 ns
Manual IO Timing Modes, Clock Mode 3 13.02 ns
Bootmode, Clock Mode 3 20.8
Q2 tw(SCLKL) Pulse duration, sclk low All Y*P-1 (1) ns
Q3 tw(SCLKH) Pulse duration, sclk high All Y*P-1 (1) ns
Q4 td(CS-SCLK) Delay time, sclk falling edge to cs active edge, CS3:0 Manual IO Timing Modes -M*P-1 (2)(3) -M*P+2 (2)(3) ns
Bootmode -M*P-2.5 (2)(3) -M*P+2.5 (2)(3)
Q5 td(SCLK-CS) Delay time, sclk falling edge to cs inactive edge, CS3:0 Manual IO Timing Modes N*P-1 (2)(3) N*P+2 (2)(3) ns
Bootmode N*P-2.5 (2)(3) N*P+2.5 (2)(3)
Q6 td(SCLK-D1) Delay time, sclk falling edge to d[0] transition Manual IO Timing Modes -1 2 ns
Bootmode -2.5 2.5
Q7 tena(CS-D1LZ) Enable time, cs active edge to d[0] driven (lo-z) All -P-3.5 -P+2.5 ns
Q8 tdis(CS-D1Z) Disable time, cs active edge to d[0] tri-stated (hi-z) All -P-2.5 -P+2.0 ns
Q9 td(SCLK-D0) Delay time, sclk first falling edge to first d[0] transition Manual IO Timing Modes, PHA=0 Only -1-P 2-P ns
Bootmode, PHA=0 Only -2.5-P 2.5-P
  1. The Y parameter is defined as follows:
    If DCLK_DIV is 0 or ODD then, Y equals 0.5.
    If DCLK_DIV is EVEN then, Y equals (DCLK_DIV / 2) / (DCLK_DIV + 1).
    For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division factor DCLK_DIV can be found in the Device TRM.
  2. P = SCLK period.
  3. M = QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.
    M = QSPI_SPI_DC_REG.DDx when Clock Mode 3.
    N = 2 when Clock Mode 0.
    N = 3 when Clock Mode 3.
AM5749 AM5748 AM5746 SPRS85v_TIMING_QSPI1_01.gifFigure 5-53 QSPI Read (Clock Mode 3)
AM5749 AM5748 AM5746 SPRS85v_TIMING_QSPI1_02.gifFigure 5-54 QSPI Read (Clock Mode 0)

CAUTION

The IO Timings provided in this section are only valid for some QSPI usage modes when the corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables found in this section.

Table 5-77 Timing Requirements for QSPI(2)(3)

No PARAMETER DESCRIPTION Mode MIN MAX UNIT
Q12 tsu(D-RTCLK) Setup time, d[3:0] valid before falling rtclk edge Manual IO Timing Modes, Clock Mode 0 2.9 ns
tsu(D-SCLK) Setup time, d[3:0] valid before falling sclk edge Manual IO Timing Modes, Clock Mode 3 5.7 ns
Boot Mode, Clock Mode 3 12.3 ns
Q13 th(RTCLK-D) Hold time, d[3:0] valid after falling rtclk edge Manual IO Timing Mode, Clock Mode 0 -0.1 ns
th(SCLK-D) Hold time, d[3:0] valid after falling sclk edge Manual IO Timing Mode, Clock Mode 3 0.1 ns
Boot Mode, Clock Mode 3 0.1 ns
Q14 tsu(D-SCLK) Setup time, final d[3:0] bit valid before final falling sclk edge Manual IO Timing Mode, Clock Mode 3 5.7-P (1) ns
Boot Mode, Clock Mode 3 12.3-P (1) ns
Q15 th(SCLK-D) Hold time, final d[3:0] bit valid after final falling sclk edge Manual IO Timing Mode, Clock Mode 3 0.1+P (1) ns
Boot Mode, Clock Mode 3 0.1+P (1) ns
  1. P = SCLK period.
  2. Clock Modes 1 and 2 are not supported.
  3. The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that launch data on the falling edge in Clock Modes 0 and 3.
AM5749 AM5748 AM5746 SPRS85v_TIMING_QSPI1_03.gifFigure 5-55 QSPI Write (Clock Mode 3)
AM5749 AM5748 AM5746 SPRS85v_TIMING_QSPI1_04.gifFigure 5-56 QSPI Write (Clock Mode 0)

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information, see chapter Control Module of the Device TRM.

Manual IO Timings Modes must be used to guarantee some IO timings for QSPI. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-78, Manual Functions Mapping for QSPI for a definition of the Manual modes.

Table 5-78 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-78 Manual Functions Mapping for QSPI

BALL BALL NAME QSPI_MODE0_MANUAL1 QSPI_MODE3_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 1
R3 gpmc_a13 0 0 0 0 CFG_GPMC_A13_IN qspi1_rtclk
T2 gpmc_a14 2149 1052 0 0 CFG_GPMC_A14_IN qspi1_d3
U2 gpmc_a15 2121 997 0 0 CFG_GPMC_A15_IN qspi1_d2
U1 gpmc_a16 2159 1134 0 0 CFG_GPMC_A16_IN qspi1_d0
U1 gpmc_a16 0 0 0 0 CFG_GPMC_A16_OUT qspi1_d0
P3 gpmc_a17 2135 1085 0 0 CFG_GPMC_A17_IN qspi1_d1
R2 gpmc_a18 0 0 151 0 CFG_GPMC_A18_OUT qspi1_sclk
T7 gpmc_a3 0 0 0 0 CFG_GPMC_A3_OUT qspi1_cs2
P6 gpmc_a4 0 0 0 0 CFG_GPMC_A4_OUT qspi1_cs3
P2 gpmc_cs2 0 0 0 0 CFG_GPMC_CS2_OUT qspi1_cs0
P1 gpmc_cs3 0 0 22 0 CFG_GPMC_CS3_OUT qspi1_cs1