ZHCSAT7H December   2012  – October 2014 AFE4490

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Supply Ramp and Power-Down Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Channel
        1. 8.3.1.1 Receiver Front-End
        2. 8.3.1.2 Ambient Cancellation Scheme
        3. 8.3.1.3 Receiver Control Signals
        4. 8.3.1.4 Receiver Timing
      2. 8.3.2 Clocking and Timing Signal Generation
      3. 8.3.3 Timer Module
        1. 8.3.3.1 Using the Timer Module
      4. 8.3.4 Receiver Subsystem Power Path
      5. 8.3.5 Transmit Section
        1. 8.3.5.1 Transmitter Power Path
        2. 8.3.5.2 LED Power Reduction During Periods of Inactivity
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC Operation and Averaging Module
        1. 8.4.1.1 Operation Without Averaging
        2. 8.4.1.2 Operation With Averaging
      2. 8.4.2 AFE Analog Output Mode (ADC Bypass Mode)
      3. 8.4.3 Diagnostics
        1. 8.4.3.1 Photodiode-Side Fault Detection
        2. 8.4.3.2 Transmitter-Side Fault Detection
        3. 8.4.3.3 Diagnostics Module
    5. 8.5 Programming
      1. 8.5.1 Serial Programming Interface
      2. 8.5.2 Reading and Writing Data
        1. 8.5.2.1 Writing Data
        2. 8.5.2.2 Reading Data
        3. 8.5.2.3 Multiple Data Reads and Writes
        4. 8.5.2.4 Register Initialization
        5. 8.5.2.5 AFE SPI Interface Design Considerations
    6. 8.6 Register Maps
      1. 8.6.1 AFE Register Description
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 商标
    3. 12.3 静电放电警告
    4. 12.4 术语表
  13. 13机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 修订历史记录

Changes from G Revision (June 2014) to H Revision

  • Changed V(ESD) parameter specification values in Absolute Maximum Ratings table Go
  • Updated AFE Register Description section to current standards: added legend and bit settings to each bit register Go

Changes from F Revision (October 2013) to G Revision

  • 添加了应用和实施、电源相关建议以及布局章节Go
  • Changed 发送 特性章节的部分描述 Go
  • Changed 集成故障诊断 特性部分的第二点描述Go
  • Changed VCM row in Pin Functions table: changed INM to INN in VCM descriptionGo
  • Changed Absolute Maximum Ratings table: changed first five rows and added TXP, TXN pins rowGo
  • Added Handling Ratings tableGo
  • Changed I-V Transimpedance Amplifier, VO(shield) parameter: changed test conditions and added minimum and maximum specifications Go
  • Changed Example value for rows t, t2, t4, t5, t7, t11, t13, t15, t17, t19, t22, t24, t26, and t28 in Table 2Go
  • Added footnote 2 to Table 2Go
  • Added footnote 2 to Figure 63Go
  • Added footnote 2 to Figure 64Go
  • Changed INN pin name in Figure 76Go
  • Changed INM to INN throughout Table 3Go
  • Added STAGE2EN1 and STG2GAIN1[2:0] in TIAGAIN registerGo
  • Changed STAGE2EN to STAGE2EN2 and STG2GAIN[2:0] to STG2GAIN2[2:0] in TIA_AMB_GAIN registerGo
  • Added last two sentences to NUMAV[7:0] description in CONTROL1: Control Register 1Go

Changes from E Revision (October 2013) to F Revision

  • Changed LED_DRV_SUP parameter in Recommended Operating Conditions tableGo
  • Changed TXM to TXN in VLED footnote of Recommended Operating Conditions tableGo
  • Changed VLED footnote and added VHR footnote to Recommended Operating Conditions tableGo
  • Changed Figure 77 (changed TXP and TXN pin names, deleted LED 1 and LED 2 pin names)Go
  • Changed Table 6 (added VHR columns to table)Go

Changes from D Revision (May 2013) to E Revision

  • Changed 具有高动态范围的接收通道特性部分，在第 4 点描述中将 2.3mA 更改为 2.3mW，在第 5 点描述中将 250µs 更改为 4msGo
  • Changed Rx，Tx 电源并从首页图中添加编辑校对Go
  • Changed Tx Power Supply column in Family and Ordering Information tableGo
  • Changed TX_REF description in Pin Descriptions tableGo
  • Changed conditions of Electrical Characteristics tableGo
  • Changed Performance, PRF parameter minimum specification in Electrical Characteristics tableGo
  • Changed PRF = 1300 Hz to PRF = 1200 Hz in test conditions for the Performance, Total integrated noise current and NFB parameters in Electrical Characteristics tableGo
  • Changed Ambient Cancellation Stage, Gain parameter in Electrical Characteristics tableGo
  • Added last two Low-Pass Filter parameters to Electrical Characteristics tableGo
  • Added Diagnostics, Diagnostics current parameter to Electrical Characteristics tableGo
  • Changed CF to C and added TX_REF capacitor to Functional Block Diagram graphicGo
  • Updated Figure 55Go
  • Changed second sentence in second paragraph of Receiver Front-End sectionGo
  • Changed third paragraph of Receiver Front-End sectionGo
  • Changed second paragraph of Ambient Cancellation Scheme sectionGo
  • Added last paragraph and Table 1 to Ambient Cancellation Scheme sectionGo
  • Updated Figure 58Go
  • Updated Figure 60Go
  • Added footnote 1 to Table 2 and changed Example column in Table 2Go
  • Changed corresponding register column description in rows t13, t15, t17, and t19 and example column values for rows t22, t24, t26, and t28 in Table 2Go
  • Updated Figure 63Go
  • Updated Figure 64Go
  • Deleted supply voltage range from RX_ANA_SUP and RX_DIG_SUP in Figure 65Go
  • Changed entire Transmit SectionGo
  • Deleted _5V from TX_CTRL_SUP and LED_DRV_SUP in Figure 68Go
  • Changed second paragraph of ADC Operation and Averaging Module sectionGo
  • Updated Equation 5 and Figure 71Go
  • Updated Figure 72Go
  • Added first paragraph of AFE Output Mode (ADC Bypass Mode) sectionGo
  • Updated Figure 75Go
  • Added last paragraph to the Diagnostics Module sectionGo
  • Added first and last sentence to Writing Data sectionGo
  • Changed second to last sentence in Writing Data sectionGo
  • Added first and last sentence to Reading Data sectionGo
  • Changed second to last sentence in Reading Data sectionGo
  • Added Multiple Data Reads and Writes sectionGo
  • Added last sentence to the AFE SPI Interface Design Considerations sectionGo
  • Added Register Control column to Table 4Go
  • Changed bits D16 and D10 in CONTROL2 row of Table 4Go
  • Changed CONTROL0 paragraph descriptionGo
  • Added note to bit D2 description of CONTROL0 registerGo
  • Changed PRPCOUNT[15:0] (bits D[15:0]) description in PRPCOUNT registerGo
  • Changed note within CLKALMPIN[2:0] (bits D[11:9]) description of CONTROL1 registerGo
  • Changed second and third columns of Table 5Go
  • Changed 001 and 011 bit settings for the STG2GAIN[2:0] bits (bits D[10:8]) in the TIA_AMB_GAIN registerGo
  • Changed description and name of bits D16 and D10 in CONTROL2 registerGo

Changes from C Revision (April 2013) to D Revision

  • Changed descriptions of RX_ANA_SUP, RX_DIG_SUP, and TX_CTRL_SUP pins in Pin Descriptions tableGo
  • Added CMRR parameter to Electrical Characteristics tableGo
  • Added External Clock, External clock input voltage and External clock input current parameters to Electrical Characteristics tableGo
  • Changed TIMING, tRESET parameter unit in Electrical Characteristics tableGo
  • Added Pin Leakage Current section to Electrical Characteristics tableGo
  • Added Supply Current, ADC bypass mode parameter to Electrical Characteristics tableGo
  • Changed Serial Interface Timing sectionGo
  • Added Figure 14Go
  • Added Figure 20Go
  • Added Figure 26Go
  • Added Figure 32Go
  • Added Figure 54Go
  • Updated Functional Block Diagram graphicGo
  • Changed name of register 15hGo
  • Added note to descriptions of LED2-ALED2VAL and LED1-ALED1VAL registersGo

Changes from B Revision (February 2013) to C Revision

  • Changed 具有高动态范围的接收通道特性部分的第一和第二点描述Go
  • Changed pin out figureGo
  • Changed ESD ratings specification values in Absolute Maximum Ratings tableGo
  • Added Performance, PSRR parameter to Electrical Characteristics tableGo
  • Changed Performance, Total integrated noise current and NFB parameters in Electrical Characteristics tableGo
  • Changed first row of Receiver Functional Block Level Specification, Total integrated noise current parameter in Electrical Characteristics tableGo
  • Changed Ambient Cancellation Stage, Gain parameter specifications in Electrical Characteristics tableGo
  • Changed Transmitter, Transmitter noise dynamic range parameter in Electrical Characteristics tableGo
  • Added External Clock, External clock input frequency parameter to Electrical Characteristics tableGo
  • Added Timing, Wake-up time from Rx power-down and Wake-up time from Tx power-down parameters to Electrical Characteristics tableGo
  • Changed Supply Current section of Electrical Characteristics tableGo
  • Changed typical specification in first row and unit in second row of Power Dissipation, PD(q) parameter in Electrical Characteristics tableGo
  • Changed Power Dissipation, After reset LED_DRV_SUP typical specification in Electrical Characteristics tableGo
  • Changed Power Dissipation, With stage 2 mode enabled LED_DRV_SUP, TX_CTRL_SUP, and RX_DIG_SUP typical specifications in Electrical Characteristics tableGo
  • Added Figure 13Go
  • Deleted Figure 11, Input-Referred Noise Current vs PLETH Current (BW = 5 Hz, PRF = 5000 Hz)Go
  • Deleted Figure 17, Input-Referred Noise Current vs PLETH Current (BW = 20 Hz, PRF = 5000 Hz)Go
  • Added Figure 24Go
  • Deleted Figure 23, Noise-Free Bits vs PLETH Current (BW = 5 Hz, PRF = 5000 Hz)Go
  • Added Figure 24Go
  • Deleted Figure 29, Noise-Free Bits vs PLETH Current (BW = 20 Hz, PRF = 5000 Hz)Go
  • Added Figure 38 through Figure 41Go
  • Added Figure 49 to Figure 53Go
  • Changed gain setting range in Receiver Front-End sectionGo
  • Changed corresponding register column description in rows t24, t26, and t28 in Table 2Go
  • Changed description of LED Power Reduction During Periods of Inactivity sectionGo
  • Changed last paragraph of AFE Analog Output Mode (ADC Bypass Mode) sectionGo
  • Updated Figure 76Go
  • Updated Figure 77Go
  • Changed LED2CONVEND register name in Table 4Go
  • Changed RESERVED1 and RESERVED2 register descriptions in Table 4Go
  • Changed description of bits D[15:0] in LED2STC registerGo
  • Changed description of bits D[15:0] in LED2ENDC, LED2LEDSTC, and LED2LEDENDC registersGo
  • Changed description of bits D[15:0] in ALED2STC, ALED2ENDC, and LED1STC registersGo
  • Changed description of bits D[15:0] in LED1ENDC, LED1LEDSTC, and LED1LEDENDC registersGo
  • Changed description of bits D[15:0] in ALED1STC, ALED1ENDC, and LED2CONVST registersGo
  • Changed description of bits D[15:0] in ALED2CONVST and ALED2CONVEND registersGo
  • Changed description of bits D[15:0] in LED1CONVST, LED1CONVEND, and ALED1CONVST registersGo
  • Changed description of bits D[15:0] in ALED1CONVEND registerGo
  • Changed RESET to RESET in ADCRSTSTCT0 and ADCRSTENDCT0 registersGo
  • Changed RESET to RESET in ADCRSTSTCT1, ADCRSTENDCT1, and ADCRSTSTCT2 registersGo
  • Changed RESET to RESET in ADCRSTENDCT2, ADCRSTSTCT3, and ADCRSTENDCT3 registersGo
  • Added footnote to Table 6Go
  • Changed bits D18 and D17 names in CONTROL2 bit registerGo
  • Added note to description of bits D[18:17] in CONTROL2 registerGo
  • Changed RESERVED1 and RESERVED2 registersGo