ZHCSFE1B June 2016 – August 2017 ADS8920B , ADS8922B , ADS8924B
PRODUCTION DATA.
This register configures the contents of the 22-bit output data word (D[21:0]).
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 0 | 0 | FPAR_LOC[1:0] | PAR_EN | DATA_VAL | |
R-0b | R-0b | R-0b | R-0b | R/W-00b | R/W-0b | R/W-0b |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | 0 | R | 0000b | Reserved bits. Reads return 0000b. |
3-2 | FPAR_LOC[1:0] | R/W | 00b | These bits control the data span for calculating the FTPAR bit (bit D[4] in the output data word). 00b = D[4] reflects even parity calculated for 4 MSB 01b = D[4] reflects even parity calculated for 8 MSB 10b = D[4] reflects even parity calculated for 12 MSB 11b = D[4] reflects even parity calculated for all 16 bits (that is, the same as FLPAR) |
1 | PAR_EN | R/W | 0b | 0b = Output data does not contain any parity information D[5] = 0 D[4] = 0 1b = Parity information is appended to the LSB of the output data D[5] = Even parity calculated on bits D[21:6] D[4] = Even parity computed on selected number of MSB of D[21:6] as per FPAR_LOC[1:0] setting See Figure 44 for further details of parity computation. |
0 | DATA_VAL | R/W | 0b | These bits control bits D[21:6] of the output data word. 0b = 16-bit conversion output 1b = 16-bit contents of the fixed-pattern registers See PATN CNTL for more details. |