8.5.42 HYSTERESIS_CH5 Register (Address = 0x34) [reset = 0xF0]
HYSTERESIS_CH5 is shown in Figure 61 and described in Table 52.
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Figure 61. HYSTERESIS_CH5 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
HIGH_THRESHOLD_CH5_LSB[3:0] |
HYSTERESIS_CH5[3:0] |
R/W-1111b |
R/W-0b |
|
Table 52. HYSTERESIS_CH5 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-4 |
HIGH_THRESHOLD_CH5_LSB[3:0] |
R/W |
1111b |
Lower 4-bits of high threshold for analog input. These bits are compared with bits 3:0 of ADC conversion result. |
3-0 |
HYSTERESIS_CH5[3:0] |
R/W |
0b |
4-bit hysteresis for high and low thresholds. This 4-bit hysteris is left shifted 3 times and applied on the lower 7-bits of the threshold. Total hysteresis = 7-bits [4-bits, 000b] |