ZHCSE76E December 2011 – December 2022 ADS1113-Q1 , ADS1114-Q1 , ADS1115-Q1
PRODUCTION DATA
The 16-bit Config register is used to control the operating mode, input selection, data rate, full-scale range, and comparator modes.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
OS | RESERVED | MODE | ||||||
R/W-1b | R/W-000010b | R/W-1b | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DR[2:0] | RESERVED | |||||||
R/W-100b | R/W-00011b |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
OS | RESERVED | PGA[2:0] | MODE | |||||
R/W-1b | R/W-000b | R/W-010b | R/W-1b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DR[2:0] | COMP_MODE | COMP_POL | COMP_LAT | COMP_QUE[1:0] | ||||
R/W-100b | R/W-0b | R/W-0b | R/W-0b | R/W-11b |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
OS | MUX[2:0] | PGA[2:0] | MODE | |||||
R/W-1b | R/W-000b | R/W-010b | R/W-1b | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DR[2:0] | COMP_MODE | COMP_POL | COMP_LAT | COMP_QUE[1:0] | ||||
R/W-100b | R/W-0b | R/W-0b | R/W-0b | R/W-11b |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | OS | R/W | 1b | Operational status or
single-shot conversion start This bit determines the operational status of the device. OS can only be written when in power-down state and has no effect when a conversion is ongoing. 0b : No effect 1b : Start a single conversion (when in power-down state) When reading: 0b : Device is currently performing a conversion 1b : Device is not currently performing a conversion |
14:12 | MUX[2:0] | R/W | 000b | Input multiplexer
configuration (ADS1115-Q1
only) These bits configure the input multiplexer. These bits serve no function on the ADS1113-Q1 and ADS1114-Q1. ADS1113-Q1 and ADS1114-Q1 always use inputs AINP = AIN0 and AINN = AIN1. 001b : AINP = AIN0 and AINN = AIN3 010b : AINP = AIN1 and AINN = AIN3 011b : AINP = AIN2 and AINN = AIN3 100b : AINP = AIN0 and AINN = GND 101b : AINP = AIN1 and AINN = GND 110b : AINP = AIN2 and AINN = GND 111b : AINP = AIN3 and AINN = GND |
11:9 | PGA[2:0] | R/W | 010b | Programmable gain
amplifier configuration These bits set the FSR of the programmable gain amplifier. These bits serve no function on the ADS1113-Q1. ADS1113-Q1 always uses FSR = ±2.048 V. 001b : FSR = ±4.096 V(1) 010b : FSR = ±2.048 V (default) 011b : FSR = ±1.024 V 100b : FSR = ±0.512 V 101b : FSR = ±0.256 V 110b : FSR = ±0.256 V 111b : FSR = ±0.256 V |
8 | MODE | R/W | 1b | Device operating
mode This bit controls the operating mode. 1b : Single-shot mode or power-down state (default) |
7:5 | DR[2:0] | R/W | 100b | Data rate These bits control the data rate setting. 001b : 16 SPS 010b : 32 SPS 011b : 64 SPS 100b : 128 SPS (default) 101b : 250 SPS 110b : 475 SPS 111b : 860 SPS |
4 | COMP_MODE | R/W | 0b | Comparator mode
(ADS1114-Q1 and
ADS1115-Q1
only) This bit configures the comparator operating mode. This bit serves no function on the ADS1113-Q1. 1b : Window comparator |
3 | COMP_POL | R/W | 0b | Comparator polarity
(ADS1114-Q1 and
ADS1115-Q1
only) This bit controls the polarity of the ALERT/RDY pin. This bit serves no function on the ADS1113-Q1. 1b : Active high |
2 | COMP_LAT | R/W | 0b | Latching comparator
(ADS1114-Q1 and
ADS1115-Q1
only) This bit controls whether the ALERT/RDY pin latches after being asserted or clears after conversions are within the margin of the upper and lower threshold values. This bit serves no function on the ADS1113-Q1. 1b : Latching comparator. The asserted ALERT/RDY pin remains latched until conversion data are read by the controller or an appropriate SMBus alert response is sent by the controller. The device responds with an address, and is the lowest address currently asserting the ALERT/RDY bus line. |
1:0 | COMP_QUE[1:0] | R/W | 11b | Comparator queue and
disable (ADS1114-Q1 and
ADS1115-Q1
only) These bits perform two functions. When set to 11, the comparator is disabled and the ALERT/RDY pin is set to a high-impedance state. When set to any other value, the ALERT/RDY pin and the comparator function are enabled, and the set value determines the number of successive conversions exceeding the upper or lower threshold required before asserting the ALERT/RDY pin. These bits serve no function on the ADS1113-Q1. 01b : Assert after two conversions 10b : Assert after four conversions 11b : Disable comparator and set ALERT/RDY pin to high-impedance (default) |